1 files changed, 9 insertions, 45 deletions
diff --git a/fuzzer/src/main/scala/firrtl/FirrtlCompileTests.scala b/fuzzer/src/main/scala/firrtl/FirrtlCompileTests.scala
index 9ee8e52b..3091e4d6 100644
--- a/fuzzer/src/main/scala/firrtl/FirrtlCompileTests.scala
+++ b/fuzzer/src/main/scala/firrtl/FirrtlCompileTests.scala
@@ -53,50 +53,14 @@ object SourceOfRandomnessGen {
   }
 }
 
-
-class FirrtlSingleModuleGenerator extends Generator[Circuit](classOf[Circuit]) {
-  override def generate(random: SourceOfRandomness, status: GenerationStatus): Circuit = {
-    implicit val r = random
-    import ExprGen._
-
-    val params = ExprGenParams(
-      maxDepth = 50,
-      maxWidth = 31,
-      generators = Seq(
-        1 -> AddDoPrimGen,
-        1 -> SubDoPrimGen,
-        1 -> MulDoPrimGen,
-        1 -> DivDoPrimGen,
-        1 -> LtDoPrimGen,
-        1 -> LeqDoPrimGen,
-        1 -> GtDoPrimGen,
-        1 -> GeqDoPrimGen,
-        1 -> EqDoPrimGen,
-        1 -> NeqDoPrimGen,
-        1 -> PadDoPrimGen,
-        1 -> ShlDoPrimGen,
-        1 -> ShrDoPrimGen,
-        1 -> DshlDoPrimGen,
-        1 -> CvtDoPrimGen,
-        1 -> NegDoPrimGen,
-        1 -> NotDoPrimGen,
-        1 -> AndDoPrimGen,
-        1 -> OrDoPrimGen,
-        1 -> XorDoPrimGen,
-        1 -> AndrDoPrimGen,
-        1 -> OrrDoPrimGen,
-        1 -> XorrDoPrimGen,
-        1 -> CatDoPrimGen,
-        1 -> BitsDoPrimGen,
-        1 -> HeadDoPrimGen,
-        1 -> TailDoPrimGen,
-        1 -> AsUIntDoPrimGen,
-        1 -> AsSIntDoPrimGen
-      )
-    )
-    params.generateSingleExprCircuit[SourceOfRandomnessGen]()
-  }
-}
+import ExprGen._
+class FirrtlCompileCircuitGenerator extends SingleExpressionCircuitGenerator (
+  ExprGenParams(
+    maxDepth = 50,
+    maxWidth = 31,
+    generators = ExprGenParams.defaultGenerators
+  )
+)
 
 @RunWith(classOf[JQF])
 class FirrtlCompileTests {
@@ -112,7 +76,7 @@ class FirrtlCompileTests {
   }
 
   @Fuzz
-  def compileSingleModule(@From(value = classOf[FirrtlSingleModuleGenerator]) c: Circuit) = {
+  def compileSingleModule(@From(value = classOf[FirrtlCompileCircuitGenerator]) c: Circuit) = {
     compile(CircuitState(c, ChirrtlForm, Seq()))
   }