diff options
Diffstat (limited to 'TODO')
| -rw-r--r-- | TODO | 13 |
1 files changed, 12 insertions, 1 deletions
@@ -3,6 +3,9 @@ ================================================ ======== Current Tasks ======== +Declared references needs to understand scope +Size of vector type must be non-negative +Check for recursively defined instances Update spec <> Add Unit Tests for each pass @@ -10,9 +13,14 @@ Add Unit Tests for each pass Push all tests entirely through Check after each pass write test that checks instance types are correctly lowered +move width inference earlier +Register should be a NODE, not a wire that is connected to, because you shouldn't be able to write to a wire that was connected to a Register? hmm.. think about this ======== Update Core ========== Add source locaters +Add exmodule +Add vptype +Add readwriteport ======== Check Passes ========== Well-formed high firrtl @@ -83,7 +91,9 @@ Convert to scala Firrtl interpreter (in scala) ======== Update Spec ======== -Add Not to spec +Look through all primops +change parser to other unknown thing for vptype? +Add optional type to node add assertions and printfs cannot connect directly to a mem (loc can never contain a mem) Front-end needs to guarantee unique names per module. @@ -108,6 +118,7 @@ Verilog backend - put stuff in posedge clock, not assign statements, for speedup Annotate mems with location stuff Coverage tests, such as statespace or specific instances (like asserts, sort of) check all predicates of whens +Generate a ROM, and index with cycle counter, and dynamically check any wire on a given cycle ======== FIRRTL++ ========= Variable size FIFOs |