diff options
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 18 |
1 files changed, 9 insertions, 9 deletions
@@ -11,20 +11,20 @@ A Firrtl compiler is constructed by chaining together these transformations, then writing the final circuit to a file. - For a detailed description of Firrtl's intermediate representation, see the document "Specification of the Firrtl Language" located in [spec/spec.pdf](https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf). + For a detailed description of Firrtl's intermediate representation, see the document "Specification of the Firrtl Language" located in [spec/spec.pdf](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf). #### Wiki Pages and Tutorials Useful information is on our wiki, located here: -* https://github.com/ucb-bar/firrtl/wiki +* https://github.com/freechipsproject/firrtl/wiki Some important pages to read, before writing your own transform: -* [Submitting Pull Requests](https://github.com/ucb-bar/firrtl/wiki/submitting-a-pull-request) -* [Understanding Firrtl's IR](https://github.com/ucb-bar/firrtl/wiki/Understanding-Firrtl-Intermediate-Representation) -* [Traversing a Circuit](https://github.com/ucb-bar/firrtl/wiki/traversing-a-circuit) -* [Common Pass Idioms](https://github.com/ucb-bar/firrtl/wiki/Common-Pass-Idioms) +* [Submitting Pull Requests](https://github.com/freechipsproject/firrtl/wiki/Submitting-a-Pull-Request) +* [Understanding Firrtl's IR](https://github.com/freechipsproject/firrtl/wiki/Understanding-Firrtl-Intermediate-Representation) +* [Traversing a Circuit](https://github.com/freechipsproject/firrtl/wiki/traversing-a-circuit) +* [Common Pass Idioms](https://github.com/freechipsproject/firrtl/wiki/Common-Pass-Idioms) -To write a Firrtl transform, please start with the tutorial here: [src/main/scala/tutorial](https://github.com/ucb-bar/firrtl/blob/master/src/main/scala/tutorial). +To write a Firrtl transform, please start with the tutorial here: [src/main/scala/tutorial](https://github.com/freechipsproject/firrtl/blob/master/src/main/scala/tutorial). To run these examples: ``` sbt assembly @@ -36,8 +36,8 @@ sbt assembly * Firrtl syntax highlighting for Vim users: https://github.com/azidar/firrtl-syntax * Firrtl syntax highlighting for Sublime Text 3 users: https://github.com/codelec/highlight-firrtl * Firrtl mode for Emacs users: https://github.com/ibm/firrtl-mode -* Chisel3, an embedded hardware DSL that generates Firrtl: https://github.com/ucb-bar/chisel3 -* Firrtl Interpreter: https://github.com/ucb-bar/firrtl-interpreter +* Chisel3, an embedded hardware DSL that generates Firrtl: https://github.com/freechipsproject/chisel3 +* Treadle, a Firrtl Interpreter: https://github.com/freechipsproject/treadle * Yosys Verilog-to-Firrtl Front-end: https://github.com/cliffordwolf/yosys #### Installation Instructions |