diff options
52 files changed, 646 insertions, 384 deletions
@@ -10,8 +10,12 @@ all-noise: all: done -install: - cd src/lib && unzip stanza.zip +install-linux: + cd src/lib && unzip stanza-linux.zip + cd src/lib/stanza && sudo ./stanza -platform linux -install /usr/local/bin/stanza + +install-mac: + cd src/lib && unzip stanza-mac.zip cd src/lib/stanza && sudo ./stanza -platform os-x -install /usr/local/bin/stanza build-deploy: @@ -35,6 +39,9 @@ errors: chisel3: cd $(test_dir)/chisel3 && lit -v . --path=$(root_dir)/utils/bin/ +refchip: + cd $(test_dir)/refchip && lit -v . --path=$(root_dir)/utils/bin/ + features: cd $(test_dir)/features && lit -v . --path=$(root_dir)/utils/bin/ @@ -13,7 +13,7 @@ #### Installation instructions (for Mac): *Disclaimer*: This project is going through development stages so there is no guarantee anything works. `git clone https://github.com/ucb-bar/firrtl # Clone repository` - `make install # Stanza installation` + `make install-mac # Stanza installation` `pip install lit # Install lit (this assumes you have pip installed)` `make build # Build firrtl` `make check # Run tests` @@ -5,9 +5,10 @@ ======== Current Tasks ======== add include support change parser to accept subword, but error ---Merge with master put clocks on accessors add clock check to high firrtl check +registers in onreset cannot have flips +add equivalence to spec Tests: Lowering for instance types with bundle ports @@ -21,14 +22,12 @@ update high/low firrtl checks need an annotation example move width inference earlier (required for subword assignment, consistent vec width inference, and supporting the new constructs of tobits/frombits) Temp elimination needs to count # uses -Declared references needs to understand scope <= check in high form check Check for recursively defined instances Names in bundles must be unique Fix reset scope Scaling Adam, could you add the following to firrtl (the program) - exit(0) on success, exit(1) on any failure - - diagnostic messages (as distinct from transformed firrtl (the code)) should go to stderr - a “-“ as a file indicates stdin for input or stdout for output so: firrtl -i - -o - fir -X flo operates like a filter. diff --git a/notes/frontend-notes.04.16.15.txt b/notes/frontend-notes.04.16.15.txt index fb7c1af9..7c571286 100644 --- a/notes/frontend-notes.04.16.15.txt +++ b/notes/frontend-notes.04.16.15.txt @@ -9,6 +9,14 @@ sub-wrap -> subw bit-and -> and bit-or -> or bit-xor -> xor +on-reset -> onreset +reg now has reset and clock +cmem/smem now has clock +accessor -> infer accessor +"Clock" is now a type, so the following declares a clock port: +module Queue : + input clk : Clock + ... diff --git a/spec/spec.pdf b/spec/spec.pdf Binary files differindex b6761494..4149c9a3 100644 --- a/spec/spec.pdf +++ b/spec/spec.pdf diff --git a/spec/spec.tex b/spec/spec.tex index 6c5038cd..3dc1716e 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -72,10 +72,10 @@ FIRRTL represents the formalized elaborated graph that the Chisel DSL produces, By including complicated constructs like vector types, bundle types, and when statements in FIRRTL, the Chisel/Scala front-end can be very light-weight. In addition, other front-ends written in languages other than Scala could be simple to write and increase external adoption. -Lowered FIRRTL represents a simplified FIRRTL circuit with structural invariants, making it essentially a netlist. +Lowered FIRRTL (LoFIRRTL) represents a simplified FIRRTL circuit with structural invariants, making it essentially a netlist. This form enables straightforward translation into another language (e.g., Verilog) by a light-weight backend. -By defining low FIRRTL as a structured subset of FIRRTL, an external user can write a transformational pass whose input is restricted, but whose output is full-featured. +By defining LoFIRRTL as a structured subset of FIRRTL, an external user can write a transformational pass whose input is restricted, but whose output is full-featured. After a custom pass, the resulting circuit should undergo lowering prior to passing it to a backend or another custom pass. \section{Acknowledgements - IN PROGRESS} @@ -102,12 +102,12 @@ We'd also like to thank our sponsors XXXX, and the University of California, Ber \pd{orientation}&= &\kws{default} \vert \kws{reverse} &\text{Orientation}\\ \pd{width} &= &\ints \vert \kw{?} &\text{Known/Unknown Integer Width}\\ \pd{stmt} &= &\info \kw{wire} \id \kw{:} \pd{type} &\text{Wire Declaration}\\ - &\vert &\info \kw{reg} \id \kw{:} \pds{type} , \ids , \pds{exp} &\text{Register Declaration}\\ - &\vert &\info \kw{smem} \id \kw{:} \pds{type} , \ids &\text{Sequential Memory Declaration}\\ - &\vert &\info \kw{cmem} \id \kw{:} \pds{type} , \ids &\text{Combinational Memory Declaration}\\ + &\vert &\info \kw{reg} \id \kw{:} \pds{type} , \pds{exp} , \pds{exp} &\text{Register Declaration}\\ + &\vert &\info \kw{smem} \id \kw{:} \pds{type} , \pds{exp} &\text{Sequential Memory Declaration}\\ + &\vert &\info \kw{cmem} \id \kw{:} \pds{type} , \pds{exp} &\text{Combinational Memory Declaration}\\ &\vert &\info \kw{inst} \id \kw{:} \id &\text{Instance Declaration}\\ &\vert &\info \kw{node} \id = \pd{exp} &\text{Node Declaration}\\ - &\vert &\info \pd{dir} \kw{accessor} \id = \pds{exp}[\pds{exp}] &\text{Accessor Declaration}\\ + &\vert &\info \pd{dir} \kw{accessor} \id = \pds{exp}[\pds{exp}] , \pds{exp} &\text{Accessor Declaration}\\ &\vert &\info \pd{exp} \kw{:=} \pd{exp} &\text{Connect}\\ &\vert &\info \kw{onreset} \pd{exp} \kw{:=} \pd{exp} &\text{OnReset Connect}\\ &\vert &\info \pd{exp} \kw{$<>$} \pd{exp} &\text{Bulk Connect}\\ @@ -231,7 +231,7 @@ Both unsigned and signed integer types require a given bit width, which may be s Unknown widths are a declaration for the width to be computed by the FIRRTL width inferencer, instead of manually given by the programmer. Zero-valued widths are currently not supported, but future versions will likely support them. -Clock types have a restricted usage, where they can only be connected to other clock types or be referenced to in the \kws{reg}, \kws{cmem}, \kws{smem}, and \kws{inst} declarations, as explained in Section \ref{statements}. +Clock types have a restricted usage, where they can only be connected to other clock types or be referenced to in the \kws{reg}, \kws{accessor}, and \kws{inst} declarations, as explained in Section \ref{statements}. They cannot be used in primitive operations. \subsection{Vector Types} @@ -314,17 +314,17 @@ The onreset statement is used to specify the initialization value for a register A memory is a stateful circuit element containing multiple elements. Unlike registers, memories can {\em only} be read from or written to through {\em accessors}. Memories always have a synchronous write, but can either be declared to be read combinatorially or synchronously. -A synchronously read memory with a given name, type and clock reference can be instantiated with the following statement. +A synchronously read memory with a given name, and type can be instantiated with the following statement. \[ \begin{aligned} -\kw{smem} \text{name } \kw{:} \pds{type},\pds{clk} \\ +\kw{smem} \text{name } \kw{:} \pds{type} \\ \end{aligned} \] -A combinatorially read memory with a given name, type and clock reference can be instantiated with the following statement. +A combinatorially read memory with a given name, and type can be instantiated with the following statement. \[ \begin{aligned} -\kw{cmem} \text{name } \kw{:} \pds{type},\pds{clk} \\ +\kw{cmem} \text{name } \kw{:} \pds{type} \\ \end{aligned} \] @@ -349,11 +349,11 @@ Consequentially, their expression cannot be a bundle type with any reversed fiel Accessors are used for either connecting to or from a vector-typed expression, from some {\em variable} index. \[ \begin{aligned} -&\pd{dir} \kw{accessor} \text{name} = \pds{exp}[\text{index}] \\ +&\pd{dir} \kw{accessor} \text{name} = \pds{exp}[\text{index}] \pds{,clk} \\ &\pd{dir} = \kws{infer} \vert \kws{read} \vert \kws{write} \vert \kw{rdwr} \\ \end{aligned} \] -Given an accessor direction, a name, an expression to access, and the index at which to access, the above statement creates an accessor that may be used for connecting to or from the expression. +Given an accessor direction, a name, an expression to access, the index at which to access, and the clock domain it is in, the above statement creates an accessor that may be used for connecting to or from the expression. The expression must have a vector type, and the index must be a variable of UInt type. A read, write, and inferred accessor is conceptually one-way; it must be consistently used to connect to, or to connect from, but not both. @@ -369,8 +369,8 @@ The accessor, \pds{writer}, acts as a memory write port that writes 42 to the in &\kw{wire} i : \kws{UInt}\kws{$<$} 5 \kws{$>$} \\ &\kw{wire} j : \kws{UInt}\kws{$<$} 5 \kws{$>$} \\ &\kw{cmem} m : \kws{UInt}\kws{$<$} 10 \kws{$>$}[10] \\ -&\kw{read} \kw{accessor} reader = m[i] \\ -&\kw{write} \kw{accessor} writer = m[j] \\ +&\kw{read} \kw{accessor} reader = m[i] , clk \\ +&\kw{write} \kw{accessor} writer = m[j] , clk \\ &writer := \kws{UInt}\kws{$<$} \kws{?} \kws{$>$}(42) \\ &\kw{node} temp = reader \\ \end{aligned} @@ -462,7 +462,7 @@ For a connection to be legal, the types of the two expressions must match exactl However, the widths of the types do not need to be equivalent. If the {\em output} expression has a smaller width than the {\em input} expression, the {\em output} is padded according to its type. -If the {\em output} expression has a larger width than the {\em input} expression, the lower bits of the {\em output} are extracted and assigned to the {\em input}. +If the {\em output} expression has a larger width than the {\em input} expression, this triggers an error. If the {\em input} width is unknown, it is inferred to be the width of the largest {\em output} that it is connected to. If the {\em output} width is unknown, it cannot inferred from this connection. @@ -1039,7 +1039,7 @@ Regardless of the type of the operand, the resultant value is a $n$-bit unsigned \section{FIRRTL Forms} -To simplify the writing of transformation passes, any FIRRTL implementation will provide a {\em resolving} pass, which resolves all types, widths, and checks the legality of the circuit, and a {\em lowering} pass, which rewrites any FIRRTL circuit into an equivalent {\em lowered form}. +To simplify the writing of transformation passes, any FIRRTL implementation will provide a {\em resolving} pass, which resolves all types, widths, and checks the legality of the circuit, and a {\em lowering} pass, which rewrites any FIRRTL circuit into an equivalent {\em lowered form}, or LoFIRRTL. \subsection{Resolved Form} @@ -1047,7 +1047,7 @@ The resolved form is guaranteed to be well-formed, meaning all restrictions to a \subsection{Lowered Form} -The lowered form is a structured subset of FIRRTL, making it a minimal representation that is convenient for low-level transforms. +The lowered form, LoFIRRTL, is a structured subset of FIRRTL, making it a minimal representation that is convenient for low-level transforms. The body of a lowered module consists of a list of declarations, connect statements, and {\em predicated single connect statements}. A predicated single connect statement is a conditional statement containing a single connect statement and no else branch. @@ -1066,7 +1066,7 @@ The following circuit is lowered: \end{aligned} \] -The following restrictions also hold for modules in lowered form. +The following restrictions also hold for modules in LoFIRRTL. \begin{itemize} \item \kws{No Nested Expressions} : @@ -1082,22 +1082,26 @@ This connect could be a predicated single connect. Other than predicated single connect statements, no other conditional statements are allowed. \item \kws{Inlined Lowered Form} : A further (and optional) pass provided by FIRRTL is the inlining pass, which recursively inlines all instances in the top-level module until the top-level module is the only remaining module in the circuit. -Inlined lowered form is essentially a flat netlist which specifies every component used in a circuit and their input connections. +Inlined LoFIRRTL is essentially a flat netlist which specifies every component used in a circuit and their input connections. \end{itemize} \section{Annotations - IN PROGRESS} +Supporting annotations is a critical piece of FIRRTL, yet is a very difficult problem to solve properly. +We are in the experimental phase of supporting annotations, and our philosophy is outlined below. +It remains to be seen whether our philosophy is correct - if not, we will certainly devise a new strategy. + \begin{enumerate}[topsep=3pt,itemsep=-0.5ex,partopsep=1ex,parsep=1ex] -\item Writing a correct compiler is difficult. -\item To make it easier, make things as brittle as possible -\item If annotations are kept in the FIRRTL graph, it is unclear how they propagate. -\item If improperly propagated, you either have annotations where they shouldn't be, or lack annotations where they should be. -\item This is impossible to detect, so turns into a silent failure -\item If annotations are used for actual manipulations of circuits later on, this could be the cause of a bug that is exceptionally hard to solve -\item Thus, annotation producer/consumer keeps external data structure mapping names to annotations -\item Pass writers must do all they can to preserve names - can provide transform for names that annotation users can run on their tables -\item If a name is mangled, the annotation consumer can ERROR. Then, they need to look at the pass to see how their annotations should propagate. +\item Writing a correct circuit is difficult - avoid silent failures at all costs. +\item If annotations are held in the graph, every pass must properly propagate all possible annotations. +\item A pass incorrectly propagating an annotation cannot be easily detected (silent failure). +\item If annotations are held in an exteral data structure mapping names to annotations, the structure must updated after every pass. +\item Incorrectly updating the structure will cause a mismatching of names between circuit components and annotation entries, which is easily detected. +\item Thus, we feel the ability to detect failure outweighs the additional burden on annotation writers. \end{enumerate} +To implement this philosophy, we encourage passes to either preserve names in the graph, use simple algorithms to transform names, or provide a rename table after a pass. +The annotation writer then updates their data structure accordingly. + \section{Concrete Syntax}\label{concrete} This section describes the text format for FIRRTL that is supported by the provided readers and writers. @@ -1177,10 +1181,10 @@ The following examples demonstrate declaring wires, registers, memories, nodes, \begin{verbatim} wire mywire : UInt<10> reg myreg : UInt<10>, clk, reset -cmem mycombmem : UInt<10>[16], clk2 -smem myseqmem : UInt<10>[16], clk2 +cmem mycombmem : UInt<10>[16] +smem myseqmem : UInt<10>[16] inst myinst : MyModule -infer accessor myaccessor = e[i] +infer accessor myaccessor = e[i],clk \end{verbatim} The connect statement is specified using the \verb|:=| operator. @@ -1286,7 +1290,28 @@ The following design decisions could potentially be changed in future spec revis \section{Questions and Answers} \begin{enumerate}[topsep=3pt,itemsep=-0.5ex,partopsep=1ex,parsep=1ex] -\item Why allow operations to allow inputs of differing widths? +\item Why are there four connect operators? +Each is needed for a particular use case - the better question is why did we chose to create multiple connect statements instead of other constructs. +Statements, as opposed to expressions, are very restricted in how they nest. +Thus, the desired supported behavior (bulk connects, resets, and subword assignments) will never be used in an arbitrary nested expression where the semantics would be unintuitive. +In addition, both the implementation and the user only needs to look at the single statement to implement it. + +\item Aren't there a lot of idiosyncrasies in FIRRTL? +The FIRRTL specification is an ongoing process, and as we push more code through it, it is likely to change. +In our opinion, the idiosyncrasies are necessary for a cohesive design (and all languages have idiosyncrasies). +It remains an unknown whether there are too many idiosyncrasies for frontend writers. +Because the spec is not frozen, we can certainly adapt it if necessary. +However, at this point, we just need to push more code through. + +\item Why have a separate construct for initializing a register? +The problem is initializing a register with a vector/bundle type, where a subset of the fields are initialized. +If the initial value is kept with the declaration, we would need a new construct to specify a subset of values of ALL (potentially) nested vector/bundle types. +It makes much more sense to separate initialization from the declaration, and use something like a := to initialize the fields/vector sub-components of the register. +The next question is why not just have users specify the initial value using their own "when reset :" statement. +This doesn't work because of last connect semantics - the user could easily clobber their initialization when statement without knowing. +Creating an onreset statement does two things: (1) specifies to the USER exactly what the reset value will be for any sub-component of a register, (2) encapsulates the reset value in a way that is easy for the implementation to special case it (so it doesn't get clobbered). + +\item Why do operations allow inputs of differing widths? We tried restricting widths, but it actually complicated width inference and made supporting front-ends with more lax width restrictions very difficult. Because there is perfectly well defined semantics, we opted to allow differing widths. In line with the Linux "funnel" philosophy of being accepting with your inputs and restrictive with your outputs. @@ -1302,12 +1327,12 @@ You need to declare wires inside whens - because generators could run within a w You should always be able to pull them into a module if we want. Now its inconsistent if you can't declare registers in the scope. -\item Why not just have low FIRRTL? -Low FIRRTL leaves out general when usage, vector and bundle types, and requires a single connect. +\item Why not just have LoFIRRTL? +LoFIRRTL leaves out general when usage, vector and bundle types, and requires a single connect. For performance backends, we will need to emit arrays and structs. If there is only a lowered circuit, we lose that ability. -We cannot simply add vector/bundle types to low FIRRTL as front-ends cannot easily remove whens without removing the complex types as well. -Instead, one will need the expressiveness in FIRRTL to write a performant backend which does not need to operate on low FIRRTL. +We cannot simply add vector/bundle types to LoFIRRTL as front-ends cannot easily remove whens without removing the complex types as well. +Instead, one will need the expressiveness in FIRRTL to write a performant backend which does not need to operate on LoFIRRTL. \item Why have asserts? Up for debate. @@ -1322,6 +1347,7 @@ We do the same thing that is done in Java, and is standard programming language \item Why did/didn't you include XXX primop? Up for debate. + \end{enumerate} \end{document} diff --git a/src/lib/stanza-linux.zip b/src/lib/stanza-linux.zip Binary files differnew file mode 100644 index 00000000..95f1b10b --- /dev/null +++ b/src/lib/stanza-linux.zip diff --git a/src/lib/stanza.zip b/src/lib/stanza-mac.zip Binary files differindex a902edd8..a902edd8 100644 --- a/src/lib/stanza.zip +++ b/src/lib/stanza-mac.zip diff --git a/src/main/stanza/bigint.stanza b/src/main/stanza/bigint.stanza index 427ad7ff..ad4a5bde 100644 --- a/src/main/stanza/bigint.stanza +++ b/src/main/stanza/bigint.stanza @@ -239,6 +239,12 @@ public defn neg! (d: BigInt, s0: BigInt) -> BigInt : public defn neg (x:BigInt) -> BigInt : op(neg!, x) +public defn neg? (x:BigInt) -> True|False : + val nw = num-words(x) + val msb = x[nw - 1] >> (length(x) - nw * 32 - 1) + if msb == 0 : false + else : true + public defn rsha! (d:BigInt, s0:BigInt, amount:Int) -> BigInt : val w = length(s0) val nw = num-words(d) @@ -362,34 +368,34 @@ defn check (msg:String, x:BigInt, e:BigInt) : defn check (msg:String, x:BigInt) : println-all([msg " " x]) -;; check("Ba ", BigIntLit({ _ }, 1)) -;; check("Bb ", BigIntLit({ _ }, 16)) -;; check("Bc ", BigIntLit({ _ }, 32)) -;; check("Bd ", BigIntLit({ _ }, 48)) -;; check("Be ", BigIntLit({ _ }, 64)) -;; check("Bf ", BigIntLit({ _ }, 65)) -;; check("B1 ", BigIntLit(1, 8)) -;; check("B2 ", BigIntLit(2, 8)) -;; check("B+ ", BigIntLit(3, 8) + BigIntLit(5, 8), BigIntLit(3 + 5, 8)) -;; check("B- ", BigIntLit(5, 8) + BigIntLit(3, 8), BigIntLit(5 + 3, 8)) -;; check("B| ", BigIntLit(5, 8) | BigIntLit(9, 8), BigIntLit(5 | 9, 8)) -;; check("B& ", BigIntLit(5, 8) & BigIntLit(9, 8), BigIntLit(5 & 9, 8)) -;; check("B^ ", BigIntLit(5, 8) ^ BigIntLit(9, 8), BigIntLit(5 ^ 9, 8)) -;; check("B< ", BigIntLit(5, 8) << 1, BigIntLit(5 << 1, 9)) -;; check("B< ", BigIntLit(5, 3) << 10, BigIntLit(5 << 1, 13)) -;; check("B< ", BigIntLit(5, 3) << 32, BigIntLit(5 << 1, 38)) -;; check("B< ", BigIntLit("b1010") << 1, BigIntLit(10 << 1, 5)) -check("S1 ", BigIntLit("hfafa") << 16, BigIntLit("hfafa0000", 32)) -check("S1 ", BigIntLit(1,32) , BigIntLit(1,32)) -check("S1 ", BigIntLit(0,32) , BigIntLit(0,32)) -;; check("B< ", BigIntLit(5, 3) << 64, BigIntLit(5 << 1, 67)) -;; check("BN ", neg(BigIntLit(2, 8)), BigIntLit(-2, 8)) -check("S2 ", BigIntLit("b11111010") << 8, BigIntLit("b1111101000000000", 16)) -check("C1 ", cat(BigIntLit("b11111010", 8), BigIntLit("b10111100", 8)), BigIntLit("b1111101010111100", 16)) -check("C3 ", cat(cat(BigIntLit("b1111"), BigIntLit("b1010")), cat(BigIntLit("b1011"), BigIntLit("b1100"))), BigIntLit("b1111101010111100", 16)) -check("C4 ", cat([BigIntLit("b1111"), BigIntLit("b1010"), BigIntLit("b1011"), BigIntLit("b1100")]), BigIntLit("b1111101010111100", 16)) -check("C5 ", BigIntLit("b101111001"), BigIntLit("b101111001")) -check("C6 ", cat(BigIntLit("b1"), BigIntLit("b01111001")), BigIntLit("b101111001")) -check("C7 ", cat(BigIntLit("b11101"), BigIntLit("b101111001")), BigIntLit("b11101101111001")) -check("C8 ", cat([BigIntLit("b11"), BigIntLit("b101"), BigIntLit("b1011"), BigIntLit("b11001")]), BigIntLit("b11101101111001")) -check("C0 ", bits(BigIntLit("b11101101111001"), 10, 1), BigIntLit("b0110111100")) +;;; check("Ba ", BigIntLit({ _ }, 1)) +;;; check("Bb ", BigIntLit({ _ }, 16)) +;;; check("Bc ", BigIntLit({ _ }, 32)) +;;; check("Bd ", BigIntLit({ _ }, 48)) +;;; check("Be ", BigIntLit({ _ }, 64)) +;;; check("Bf ", BigIntLit({ _ }, 65)) +;;; check("B1 ", BigIntLit(1, 8)) +;;; check("B2 ", BigIntLit(2, 8)) +;;; check("B+ ", BigIntLit(3, 8) + BigIntLit(5, 8), BigIntLit(3 + 5, 8)) +;;; check("B- ", BigIntLit(5, 8) + BigIntLit(3, 8), BigIntLit(5 + 3, 8)) +;;; check("B| ", BigIntLit(5, 8) | BigIntLit(9, 8), BigIntLit(5 | 9, 8)) +;;; check("B& ", BigIntLit(5, 8) & BigIntLit(9, 8), BigIntLit(5 & 9, 8)) +;;; check("B^ ", BigIntLit(5, 8) ^ BigIntLit(9, 8), BigIntLit(5 ^ 9, 8)) +;;; check("B< ", BigIntLit(5, 8) << 1, BigIntLit(5 << 1, 9)) +;;; check("B< ", BigIntLit(5, 3) << 10, BigIntLit(5 << 1, 13)) +;;; check("B< ", BigIntLit(5, 3) << 32, BigIntLit(5 << 1, 38)) +;;; check("B< ", BigIntLit("b1010") << 1, BigIntLit(10 << 1, 5)) +;check("S1 ", BigIntLit("hfafa") << 16, BigIntLit("hfafa0000", 32)) +;check("S1 ", BigIntLit(1,32) , BigIntLit(1,32)) +;check("S1 ", BigIntLit(0,32) , BigIntLit(0,32)) +;;; check("B< ", BigIntLit(5, 3) << 64, BigIntLit(5 << 1, 67)) +;;; check("BN ", neg(BigIntLit(2, 8)), BigIntLit(-2, 8)) +;check("S2 ", BigIntLit("b11111010") << 8, BigIntLit("b1111101000000000", 16)) +;check("C1 ", cat(BigIntLit("b11111010", 8), BigIntLit("b10111100", 8)), BigIntLit("b1111101010111100", 16)) +;check("C3 ", cat(cat(BigIntLit("b1111"), BigIntLit("b1010")), cat(BigIntLit("b1011"), BigIntLit("b1100"))), BigIntLit("b1111101010111100", 16)) +;check("C4 ", cat([BigIntLit("b1111"), BigIntLit("b1010"), BigIntLit("b1011"), BigIntLit("b1100")]), BigIntLit("b1111101010111100", 16)) +;check("C5 ", BigIntLit("b101111001"), BigIntLit("b101111001")) +;check("C6 ", cat(BigIntLit("b1"), BigIntLit("b01111001")), BigIntLit("b101111001")) +;check("C7 ", cat(BigIntLit("b11101"), BigIntLit("b101111001")), BigIntLit("b11101101111001")) +;check("C8 ", cat([BigIntLit("b11"), BigIntLit("b101"), BigIntLit("b1011"), BigIntLit("b11001")]), BigIntLit("b11101101111001")) +;check("C0 ", bits(BigIntLit("b11101101111001"), 10, 1), BigIntLit("b0110111100")) diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index c087e66e..1ca84035 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -9,7 +9,7 @@ defpackage firrtl/compiler : import firrtl/ir-utils public defstruct StandardFlo <: Compiler : - file: String with: (as-method => true) + with-output : (() -> False) -> False with: (as-method => true) public defmethod passes (c:StandardFlo) -> List<Pass> : to-list $ [ RemoveSpecialChars() @@ -35,11 +35,11 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : RemoveSpecialChars() CheckHighForm() CheckLowForm() - Flo(file(c)) + Flo(with-output(c)) ] public defstruct StandardVerilog <: Compiler : - file: String with: (as-method => true) + with-output : (() -> False) -> False with: (as-method => true) public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ RemoveSpecialChars() @@ -66,9 +66,10 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : CheckHighForm() CheckLowForm() CheckInitialization() - Verilog(file(c)) + Verilog(with-output(c)) ] + ;============= DRIVER ====================================== public defn run-passes (c:Circuit,comp:Compiler) : run-passes(c,passes(comp)) @@ -82,20 +83,20 @@ public defn run-passes (c:Circuit,ls:List<Pass>) : var t = start-time val time-table = Vector<[String,Int]>() for p in ls do : - println-all(STANDARD-OUTPUT,["Starting " name(p)]) + println-all(["Starting " name(p)]) if PRINT-CIRCUITS : println(name(p)) c* = pass(p)(c*) if PRINT-CIRCUITS : print(c*) val current-time = to-int(to-string(current-time-us() / to-long(1000))) - println-all(STANDARD-OUTPUT,["Finished " name(p)]) - println-all(STANDARD-ERROR,["Milliseconds since start: " current-time - start-time]) - println-all(STANDARD-ERROR,["Milliseconds for this pass: " current-time - t]) - println-all(STANDARD-ERROR,["\n"]) + println-all(["Finished " name(p)]) + println-all(["Milliseconds since start: " current-time - start-time]) + println-all(["Milliseconds for this pass: " current-time - t]) + println-all(["\n"]) add(time-table,[name(p), current-time - t]) t = current-time - println(STANDARD-ERROR,"===== Time Breakdown =====") + println("===== Time Breakdown =====") for x in time-table do : - println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%"]) - println(STANDARD-ERROR,"==========================") + println-all([x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%"]) + println("==========================") println("Done!") diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza index 4d63a173..85275c94 100644 --- a/src/main/stanza/custom-compiler.stanza +++ b/src/main/stanza/custom-compiler.stanza @@ -9,7 +9,7 @@ defpackage firrtl/custom-compiler : import firrtl/custom-passes public defstruct InstrumentedVerilog <: Compiler : - file: String with: (as-method => true) + with-output: (() -> False) -> False with: (as-method => true) args: List<String> public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : to-list $ [ @@ -36,7 +36,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> : RemoveSpecialChars() CheckHighForm() CheckLowForm() - Verilog(file(c)) + Verilog(with-output(c)) ] diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 6cdd1dca..8727f762 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -45,38 +45,40 @@ public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-for public defmethod name (b:CheckHighForm) -> String : "High Form Check" public defmethod short-name (b:CheckHighForm) -> String : "high-form-check" +var mname = "" + ;----------------- Errors ------------------------ defn NotUnique (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Reference " name " does not have a unique name."] + [info ": [module " mname "] Reference " name " does not have a unique name."] defn IsPrefix (info:FileInfo, prefix:Symbol) : PassException $ string-join $ - [info ": Symbol " prefix " is a prefix."] - + [info ": [module " mname "] Symbol " prefix " is a prefix."] + defn InvalidLOC (info:FileInfo) : PassException $ string-join $ - [info ": Invalid connect to an expression that is not a reference or a WritePort."] + [info ": [module " mname "] Invalid connect to an expression that is not a reference or a WritePort."] defn NegUInt (info:FileInfo) : PassException $ string-join $ - [info ": UIntValue cannot be negative."] + [info ": [module " mname "] UIntValue cannot be negative."] defn UndeclaredReference (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Reference " name " is not declared."] + [info ": [module " mname "] Reference " name " is not declared."] defn MemWithFlip (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Memory " name " cannot be a bundle type with flips."] + [info ": [module " mname "] Memory " name " cannot be a bundle type with flips."] defn InvalidSubfield (info:FileInfo) : PassException $ string-join $ - [info ": Invalid subfield access to non-reference."] + [info ": [module " mname "] Invalid subfield access to non-reference."] defn InvalidIndex (info:FileInfo) : PassException $ string-join $ - [info ": Invalid index access to non-reference."] + [info ": [module " mname "] Invalid index access to non-reference."] defn NoTopModule (info:FileInfo, name:Symbol) : PassException $ string-join $ @@ -92,19 +94,19 @@ defn ModuleNotDefined (info:FileInfo, name:Symbol) : defn IncorrectNumArgs (info:FileInfo, op:Symbol, n:Int) : PassException $ string-join $ - [info ": Primop " op " requires " n " expression arguments."] + [info ": [module " mname "] Primop " op " requires " n " expression arguments."] defn IncorrectNumConsts (info:FileInfo, op:Symbol, n:Int) : PassException $ string-join $ - [info ": Primop " op " requires " n " integer arguments."] + [info ": [module " mname "] Primop " op " requires " n " integer arguments."] defn NegWidth (info:FileInfo) : PassException $ string-join $ - [info ": Width cannot be negative."] + [info ": [module " mname "] Width cannot be negative."] defn NegVecSize (info:FileInfo) : PassException $ string-join $ - [info ": Vector type size cannot be negative."] + [info ": [module " mname "] Vector type size cannot be negative."] ;---------------- Helper Functions -------------- defn has-flip? (t:Type) -> True|False : @@ -218,6 +220,8 @@ defn check-high-form-primop (e:DoPrim, errors:Vector<PassException>,info:FileInf GREATER-EQ-OP : correct-num(2,0) EQUAL-OP : correct-num(2,0) NEQUAL-OP : correct-num(2,0) + EQUIV-OP : correct-num(2,0) + NEQUIV-OP : correct-num(2,0) MUX-OP : correct-num(3,0) PAD-OP : correct-num(1,1) AS-UINT-OP : correct-num(1,0) @@ -278,7 +282,7 @@ public defn check-high-form (c:Circuit) -> Circuit : (e) : add(errors,InvalidIndex(info)) (e:DoPrim) : check-high-form-primop(e,errors,info) (e:UIntValue) : - if value(e) < BigIntLit("h0",length(value(e))) : add(errors,NegUInt(info)) + if neg?(value(e)) : add(errors,NegUInt(info)) (e) : false map(check-high-form-w{info,_:Width},e) map(check-high-form-t{info,_:Type},e) @@ -335,6 +339,7 @@ public defn check-high-form (c:Circuit) -> Circuit : s }() defn check-high-form-m (m:Module) -> False : + mname = name(m) val names = HashTable<Symbol,True>(symbol-hash) val mnames = HashTable<Symbol,True>(symbol-hash) for m in modules(c) do : @@ -382,15 +387,15 @@ public defmethod short-name (b:CheckKinds) -> String : "check-kinds" ;----------------- Errors --------------------- defn NotMem (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Reference " name " must be a mem."] + [info ": [module " mname "] Reference " name " must be a mem."] defn IsMem (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Reference " name " cannot be a mem."] + [info ": [module " mname "] Reference " name " cannot be a mem."] defn OnResetNotReg (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Illegal on-reset to non-reg reference " name "."] + [info ": [module " mname "] Illegal on-reset to non-reg reference " name "."] ;----------------- Check Kinds Pass --------------------- ; I may have been overeager in looking for places where mems can't be, as mems are guaranteed to have a vector @@ -437,6 +442,7 @@ public defn check-kinds (c:Circuit) -> Circuit : do(check-kinds-s,s) for m in modules(c) do : + mname = name(m) match(m) : (m:ExModule) : false (m:InModule) : check-kinds-s(body(m)) @@ -463,55 +469,55 @@ public defmethod short-name (b:CheckTypes) -> String : "check-types" ;----------------- Errors --------------------- defn SubfieldNotInBundle (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Subfield " name " is not in bundle."] + [info ": [module " mname "] Subfield " name " is not in bundle."] defn SubfieldOnNonBundle (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Subfield " name " is accessed on a non-bundle."] + [info ": [module " mname "] Subfield " name " is accessed on a non-bundle."] defn IndexTooLarge (info:FileInfo, value:Int) : PassException $ string-join $ - [info ": Index with value " value " is too large."] + [info ": [module " mname "] Index with value " value " is too large."] defn IndexOnNonVector (info:FileInfo) : PassException $ string-join $ - [info ": Index illegal on non-vector type."] + [info ": [module " mname "] Index illegal on non-vector type."] defn IndexNotUInt (info:FileInfo) : PassException $ string-join $ - [info ": Index is not of UIntType."] + [info ": [module " mname "] Index is not of UIntType."] defn EnableNotUInt (info:FileInfo) : PassException $ string-join $ - [info ": Enable is not of UIntType."] + [info ": [module " mname "] Enable is not of UIntType."] defn InvalidConnect (info:FileInfo) : PassException $ string-join $ - [info ": Type mismatch."] + [info ": [module " mname "] Type mismatch."] defn PredNotUInt (info:FileInfo) : PassException $ string-join $ - [info ": Predicate not a UIntType."] + [info ": [module " mname "] Predicate not a UIntType."] defn OpNotGround (info:FileInfo, op:Symbol) : PassException $ string-join $ - [info ": Primop " op " cannot operate on non-ground types."] + [info ": [module " mname "] Primop " op " cannot operate on non-ground types."] defn OpNotUInt (info:FileInfo, op:Symbol,e:Symbol) : PassException $ string-join $ - [info ": Primop " op " requires argument " e " to be a UInt type."] + [info ": [module " mname "] Primop " op " requires argument " e " to be a UInt type."] defn OpNotAllUInt (info:FileInfo, op:Symbol) : PassException $ string-join $ - [info ": Primop " op " requires all arguments to be UInt type."] + [info ": [module " mname "] Primop " op " requires all arguments to be UInt type."] defn OpNotAllSameType (info:FileInfo, op:Symbol) : PassException $ string-join $ - [info ": Primop " op " requires all operands to have the same type."] + [info ": [module " mname "] Primop " op " requires all operands to have the same type."] defn NodeWithFlips (info:FileInfo) : PassException $ string-join $ - [info ": Node cannot be a bundle type with flips."] + [info ": [module " mname "] Node cannot be a bundle type with flips."] ;---------------- Helper Functions -------------- @@ -568,8 +574,10 @@ defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) - LESS-EQ-OP : false GREATER-OP : false GREATER-EQ-OP : false - EQUAL-OP : all-same-type(args(e)) - NEQUAL-OP : all-same-type(args(e)) + EQUAL-OP : false + NEQUAL-OP : false + EQUIV-OP : all-same-type(args(e)) + NEQUIV-OP : all-same-type(args(e)) MUX-OP : all-same-type(tail(args(e))) is-uint(head(args(e))) @@ -618,6 +626,8 @@ public defn check-types (c:Circuit) -> Circuit : match(map(check-types-e{info(s),_},s)) : (s:Connect) : if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s))) + (s:Connect) : + if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s))) (s:OnReset) : if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s))) (s:Conditionally) : @@ -628,6 +638,7 @@ public defn check-types (c:Circuit) -> Circuit : s }() for m in modules(c) do : + mname = name(m) match(m) : (m:ExModule) : false (m:InModule) : check-types-s(body(m)) @@ -648,11 +659,11 @@ public defmethod short-name (b:CheckGenders) -> String : "check-genders" ;----------------- Errors --------------------- defn WrongGender (info:FileInfo,expr:Symbol,wrong:Symbol,right:Symbol) : PassException $ string-join $ - [info ": Expression " expr "has gender " wrong " but requires gender " right "."] + [info ": [module " mname "] Expression " expr " is used as a " wrong " but can only be used as a " right "."] defn InferDirection (info:FileInfo,name:Symbol) : PassException $ string-join $ - [info ": Accessor " name " has a direction that requires inference."] + [info ": [module " mname "] Accessor " name " has a direction that requires inference."] ;---------------- Helper Functions -------------- defn dir-to-gender (d:PortDirection) -> Gender : @@ -667,14 +678,24 @@ defn gender (s:DefAccessor) -> Gender : INFER : UNKNOWN-GENDER RDWR : BI-GENDER +defn as-srcsnk (g:Gender) -> Symbol : + switch {_ == g} : + MALE : `source + FEMALE : `sink + UNKNOWN-GENDER : `unknown + BI-GENDER : `sourceOrSink + ;----------------- Check Genders Pass --------------------- public defn check-genders (c:Circuit) -> Circuit : val errors = Vector<PassException>() defn check-gender (info:FileInfo,genders:HashTable<Symbol,Gender>,e:Expression,right:Gender) -> False : val gender = get-gender(e,genders) + ;println(gender) + ;println(right) + ;println(right == gender) if gender != right and gender != BI-GENDER: - add(errors,WrongGender(info,to-symbol(e),to-symbol(gender),to-symbol(right))) + add(errors,WrongGender(info,to-symbol(e),as-srcsnk(right),as-srcsnk(gender))) defn get-gender (e:Expression,genders:HashTable<Symbol,Gender>) -> Gender : match(e) : @@ -701,6 +722,7 @@ public defn check-genders (c:Circuit) -> Circuit : defn check-genders-s (s:Stmt,genders:HashTable<Symbol,Gender>) -> False : do(check-genders-e{info(s),_:Expression,genders},s) + do(check-genders-s{_:Stmt,genders},s) match(s) : (s:DefWire) : genders[name(s)] = BI-GENDER (s:DefRegister) : genders[name(s)] = BI-GENDER @@ -730,6 +752,7 @@ public defn check-genders (c:Circuit) -> Circuit : for m in modules(c) do : + mname = name(m) val genders = HashTable<Symbol,Gender>(symbol-hash) for p in ports(m) do : genders[name(p)] = dir-to-gender(direction(p)) @@ -756,27 +779,27 @@ public defmethod short-name (b:CheckLowForm) -> String : "low-form-check" ;----------------- Errors ------------------------ defn InvalidVec (info:FileInfo,name:Symbol) : PassException $ string-join $ - [info ": Expression " name " has an illegal vector type."] + [info ": [module " mname "] Expression " name " has an illegal vector type."] defn InvalidBundle (info:FileInfo,name:Symbol) : PassException $ string-join $ - [info ": Expression " name " has an illegal bundle type."] + [info ": [module " mname "] Expression " name " has an illegal bundle type."] defn NoWhen (info:FileInfo) : PassException $ string-join $ - [info ": Illegal when statement. No when statements with multiple statements are allowed in low firrtl."] + [info ": [module " mname "] Illegal when statement. No when statements with multiple statements are allowed in low firrtl."] defn SingleAssignment (info:FileInfo,name:Symbol) : PassException $ string-join $ - [info ": Illegal assignment to " name ". Wires can only be assigned to once."] + [info ": [module " mname "] Illegal assignment to " name ". Wires can only be assigned to once."] defn NoOnReset (info:FileInfo) : PassException $ string-join $ - [info ": Invalid use of on-reset. No on-resets are allowed in low firrtl."] + [info ": [module " mname "] Invalid use of on-reset. No on-resets are allowed in low firrtl."] defn NoBulkConnect (info:FileInfo) : PassException $ string-join $ - [info ": Invalid use of <>. No <>'s are allowed in low firrtl."] + [info ": [module " mname "] Invalid use of <>. No <>'s are allowed in low firrtl."] ;---------------- Helper Functions -------------- @@ -843,6 +866,7 @@ public defn check-low-form (c:Circuit) -> Circuit : false for m in modules(c) do : + mname = name(m) check-low-form-m(m) throw(PassExceptions(errors)) when not empty?(errors) c @@ -860,7 +884,7 @@ public defmethod short-name (b:CheckInitialization) -> String : "check-init" defn RefNotInitialized (info:FileInfo, name:Symbol) : PassException $ string-join $ - [info ": Reference " name " is not fully initialized."] + [info ": [module " mname "] Reference " name " is not fully initialized."] ;------------ Helper Functions ------------- @@ -903,6 +927,7 @@ public defn check-init (c:Circuit) : (v) : false for m in modules(c) do : + mname = name(m) match(m) : (m:InModule) : check-init-m(m) (m) : false diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 822b8610..8de688d7 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -50,6 +50,8 @@ public val GREATER-OP = new PrimOp public val GREATER-EQ-OP = new PrimOp public val NEQUAL-OP = new PrimOp public val EQUAL-OP = new PrimOp +public val NEQUIV-OP = new PrimOp +public val EQUIV-OP = new PrimOp public val MUX-OP = new PrimOp public val PAD-OP = new PrimOp public val AS-UINT-OP = new PrimOp diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 9762966b..e5aad984 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -24,6 +24,7 @@ defpackage firrtl-main : import verse import firrtl/parser import firrtl/passes + import firrtl/ir2 import firrtl/lexer import stz/parser import firrtl/ir-utils @@ -54,37 +55,86 @@ defn main () : val args = commandline-arguments() var input = false var output = false + var firms = Vector<String>() var compiler = false val pass-names = Vector<String>() val pass-args = Vector<String>() var printvars = "" + var last-s = "" + + val prev-out = CURRENT-OUTPUT-STREAM + CURRENT-OUTPUT-STREAM = STANDARD-ERROR + + for (s in args, i in 0 to false) do : - if s == "-i" : input = args[i + 1] - if s == "-o" : output = args[i + 1] - if s == "-x" : add(pass-names,args[i + 1]) - if s == "-X" : compiler = args[i + 1] - if s == "-p" : printvars = args[i + 1] - if s == "-s" : add(pass-args,args[i + 1]) + if s == "-i" : last-s = s + else if s == "-o" : last-s = s + else if s == "-x" : last-s = s + else if s == "-X" : last-s = s + else if s == "-p" : last-s = s + else if s == "-s" : last-s = s + else if s == "-m" : last-s = s + else : + if last-s == "-i" : input = args[i] + if last-s == "-o" : output = args[i] + if last-s == "-x" : add(pass-names,args[i]) + if last-s == "-X" : compiler = args[i] + if last-s == "-p" : printvars = args[i] + if last-s == "-s" : add(pass-args,args[i]) + if last-s == "-m" : add(firms,args[i]) + + var with-output = + fn (f:()->False) : + val prev-stream = CURRENT-OUTPUT-STREAM + CURRENT-OUTPUT-STREAM = STANDARD-OUTPUT + f() + CURRENT-OUTPUT-STREAM = prev-stream if input == false : error("No input file provided. Use -i flag.") - if output == false : - error("No output file provided. Use -o flag.") + if output != false and output != "-": + with-output = + fn (f:()->False) : + val prev-stream = CURRENT-OUTPUT-STREAM + val out-stream = FileOutputStream(output as String) + CURRENT-OUTPUT-STREAM = out-stream + f() + CURRENT-OUTPUT-STREAM = prev-stream + close(out-stream) + if compiler == false and length(pass-names) == 0 : error("Must specify a compiler. Use -X flag.") val lexed = lex-file(input as String) - val c = parse-firrtl(lexed) + val circuit = parse-firrtl(lexed) + + val modules* = Vector<Module>() + for m in modules(circuit) do : + add(modules*,m) + + val included-c = + for m in firms map : + val lexed = lex-file(m as String) + parse-firrtl(lexed) + + for c in included-c do : + for m in modules(c) do : + add(modules*,m) + + val circuit* = Circuit(info(circuit),to-list(modules*),main(circuit)) + set-printvars!(to-list(printvars)) if compiler == false : - run-passes(c,get-passes(to-list(pass-names))) + run-passes(circuit*,get-passes(to-list(pass-names))) else : switch {_ == compiler} : - "flo" : run-passes(c,StandardFlo(output as String)) - "verilog" : run-passes(c,StandardVerilog(output as String)) - "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args)) + "flo" : run-passes(circuit*,StandardFlo(with-output)) + "verilog" : run-passes(circuit*,StandardVerilog(with-output)) + "verilute" : run-passes(circuit*,InstrumentedVerilog(with-output,to-list $ pass-args)) else : error("Invalid compiler flag") + CURRENT-OUTPUT-STREAM = prev-out + main() diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index f4b453ba..7ef942f2 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -9,8 +9,8 @@ defpackage firrtl/flo : ;============= Flo Backend ================ public defstruct Flo <: Pass : - file : String -public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{file(b),_} + with-output: (() -> False) -> False +public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{with-output(b),_} public defmethod name (b:Flo) -> String : "To Flo" definterface FloKind @@ -38,6 +38,8 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : LESS-EQ-OP : "lte" ;; todo: swap args GREATER-OP : "lt" ;; todo: swap args GREATER-EQ-OP : "lte" ;; todo: signed version + NEQUIV-OP : "neq" + EQUIV-OP : "eq" NEQUAL-OP : "neq" EQUAL-OP : "eq" MUX-OP : "mux" @@ -61,12 +63,13 @@ defn flo-op-name (op:PrimOp, args:List<Expression>) -> String : else : error $ string-join $ ["Unable to print Primop: " op] -defn sane-width (wd:Width) -> Int : +defn sane-width (wd:Width) -> Int|Long : match(wd) : (w:IntWidth) : max(1, width(w)) + (w:LongWidth) : max(to-long(1), width(w)) (w) : error(string-join(["Unknown width: " w])) -defn prim-width (type:Type) -> Int : +defn prim-width (type:Type) -> Int|Long : match(type) : (t:UIntType) : sane-width(width(t)) (t:SIntType) : sane-width(width(t)) @@ -193,8 +196,9 @@ defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) : OUTPUT : flokinds[name(port)] = FOutputPortKind() emit-s(body(m), flokinds, name(m),sh) -public defn emit-flo (file:String, c:Circuit) : - with-output-file{file, _} $ fn () : +public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) : + with-output $ { emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule)) false + } c diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index fdf4c383..34d9ef57 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -27,6 +27,15 @@ defn* apply-suffix-ops (x, fs:List) : if empty?(fs) : x else : apply-suffix-ops(head(fs)(x), tail(fs)) +defn parse-stmts (forms:List) : + val cs = Vector<Stmt>() + defn* loop (forms:List) : + match-syntax(forms) : + () : to-list(cs) + (?s:#stmt ?rest ...) : (add(cs, s), loop(rest)) + (?rest ...) : FPE(rest, "Expected a statement here.") + loop(forms) + ;======== Parser Utilities ============== defn atom? (x) : unwrap-token(x) not-typeof List @@ -47,6 +56,8 @@ OPERATORS[`gt] = GREATER-OP OPERATORS[`geq] = GREATER-EQ-OP OPERATORS[`eq] = EQUAL-OP OPERATORS[`neq] = NEQUAL-OP +OPERATORS[`eqv] = EQUIV-OP +OPERATORS[`neqv] = NEQUIV-OP OPERATORS[`mux] = MUX-OP OPERATORS[`pad] = PAD-OP OPERATORS[`neg] = NEG-OP @@ -167,6 +178,8 @@ defsyntax firrtl : ;Main Module Production defrule module : + ;module = (module ?name:#id! #:! (?ps:#port ... ?rest ...)) : + ; InModule(first-info(form), name, ps, Begin(parse-stmts(rest))) module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) : if not empty?(rest) : FPE(rest, "Expected a statement here.") @@ -235,6 +248,8 @@ defsyntax firrtl : stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y) stmt = (?x:#exp <> ?y:#exp!) : BulkConnect(first-info(form),x, y) + ;stmt = ((?s:#stmt ?rest ...)) : + ; Begin(List(s, parse-stmts(rest))) stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) : if not empty?(rest) : FPE(rest, "Expected a statement here.") diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 0118c73b..7bb7ff01 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -61,7 +61,7 @@ public defn PassExceptions (xs:Streamable<PassException>) : public definterface Compiler public defmulti passes (c:Compiler) -> List<Pass> -public defmulti file (c:Compiler) -> String +public defmulti with-output (c:Compiler) -> ((() -> False) -> False) public definterface Pass public defmulti pass (p:Pass) -> (Circuit -> Circuit) @@ -86,9 +86,13 @@ public defn abs (x:Long) -> Long : if x < to-long(0) : to-long(0) - x else : x -;public defn to-int (x:Long) -> Int : - ;if x > to-long(2147483647) or x < to-long(–2147483648) : error("Long too big to convert to Int") - ;else : x + 0 +public defn max (x:Long,y:Long) -> Long : + if x < y : y + else : x + +public defn to-int (x:Long) -> Int : + if x > to-long(2147483647) or x < to-long(-2147483648) : error("Long too big to convert to Int") + else : to-int(to-string(x)) ;============== PRINTERS =================================== @@ -135,6 +139,8 @@ defmethod print (o:OutputStream, op:PrimOp) : LESS-EQ-OP : "leq" GREATER-OP : "gt" GREATER-EQ-OP : "geq" + EQUIV-OP : "eqv" + NEQUIV-OP : "neqv" EQUAL-OP : "eq" NEQUAL-OP : "neq" MUX-OP : "mux" diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index db1a056e..d5034f8a 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -815,6 +815,9 @@ defn resolve-genders (c:Circuit) : defn resolve-genders (m:Module, c:Circuit) -> Module : val genders = HashTable<Symbol,Gender>(symbol-hash) + ;for p in ports(m) do : + ;if direction(p) == INPUT : genders[name(p)] = MALE + ;else : genders[name(p)] = FEMALE resolve-module(m,genders) Circuit(info(c),modules*, main(c)) where : @@ -1134,7 +1137,7 @@ public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexe defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt : defn equality (e1:Expression,e2:Expression) -> Expression : - DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth())) + DoPrim(EQUIV-OP,list(e1,e2),List(),UIntType(UnknownWidth())) defn get-name (e:Expression) -> Symbol : match(e) : (e:WRef) : symbol-join([name(e) temp-delin]) @@ -1254,7 +1257,7 @@ defn OR (e1:Expression,e2:Expression) -> Expression : defn NOT (e1:Expression) -> Expression : if e1 == one : zero else if e1 == zero : one - else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1))) + else : DoPrim(EQUIV-OP,list(e1,zero),list(),UIntType(IntWidth(1))) defn children (e:Expression) -> List<Expression> : val es = Vector<Expression>() @@ -1504,15 +1507,14 @@ defn mark-referenced (referenced?:HashTable<Symbol,True>, s:Stmt) -> False : map(mark-referenced-e,s) false -defn mark-referenced (referenced?:HashTable<Symbol,True>, sv:SymbolicValue) -> False : +defn mark-referenced (referenced?:HashTable<Symbol,True>, sv:SymbolicValue) -> SymbolicValue : defn mark-referenced-e (e:Expression) -> Expression : match(map(mark-referenced-e,e)) : (e:WRef) : referenced?[name(e)] = true e (e) : e - map(mark-referenced-e,sv) - false + map{mark-referenced-e,_} $ map(mark-referenced{referenced?,_:SymbolicValue},sv) defn is-referenced? (referenced?:HashTable<Symbol,True>, s:Stmt) -> True|False : match(s) : @@ -1814,8 +1816,8 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : (w1,w2) : w (w:ExpWidth) : match(arg1(w)) : - (w1:IntWidth) : LongWidth(pow(to-long(2),to-long(width(w1) - 1))) - (w1:LongWidth) : LongWidth(pow(to-long(2),minus(width(w1), to-long(1)))) + (w1:IntWidth) : LongWidth(pow(to-long(2),to-long(width(w1))) - to-long(1)) + (w1:LongWidth) : LongWidth(pow(to-long(2),width(w1)) - to-long(1)) (w1) : w (w) : w defn substitute (w:Width,h:HashTable<Symbol,Width>) -> Width : diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 0e343d74..f7eb6d04 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -39,6 +39,8 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim : GREATER-EQ-OP : DoPrim(GREATER-EQ-OP,args(e),consts(e),u()) EQUAL-OP : DoPrim(EQUAL-OP,args(e),consts(e),u()) NEQUAL-OP : DoPrim(NEQUAL-OP,args(e),consts(e),u()) + EQUIV-OP : DoPrim(EQUIV-OP,args(e),consts(e),u()) + NEQUIV-OP : DoPrim(NEQUIV-OP,args(e),consts(e),u()) MUX-OP : DoPrim(MUX-OP,args(e),consts(e),of-type(args(e)[1])) PAD-OP : DoPrim(PAD-OP,args(e),consts(e),of-type(args(e)[0])) AS-UINT-OP : DoPrim(AS-UINT-OP,args(e),consts(e),u()) @@ -98,6 +100,8 @@ public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : GREATER-EQ-OP : IntWidth(1) EQUAL-OP : IntWidth(1) NEQUAL-OP : IntWidth(1) + EQUIV-OP : IntWidth(1) + NEQUIV-OP : IntWidth(1) MUX-OP : add(v,WGeq(IntWidth(1),width!(args(e)[0]))) add(v,WGeq(width!(args(e)[0]),IntWidth(1))) diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza index ca47170b..cbfd6d8b 100644 --- a/src/main/stanza/verilog.stanza +++ b/src/main/stanza/verilog.stanza @@ -7,8 +7,8 @@ defpackage firrtl/verilog : ;============ VERILOG ============== public defstruct Verilog <: Pass : - file : String -public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{file(b),_} + with-output: (() -> False) -> False +public defmethod pass (b:Verilog) -> (Circuit -> Circuit) : emit-verilog{with-output(b),_} public defmethod name (b:Verilog) -> String : "To Verilog" public defmethod short-name (b:Verilog) -> String : "To Verilog" @@ -60,7 +60,10 @@ defn emit-signed-if-any (e:Expression,ls:List<Expression>) -> String : for x in ls do : if type(x) typeof SIntType : signed? = true if not signed? : emit(e) - else : string-join(["$signed(" emit(e) ")"]) + else : + match(type(e)) : + (t:SIntType) : string-join(["$signed(" emit(e) ")"]) + (t:UIntType) : string-join(["$signed({1'b0," emit(e) "})"]) defn emit (e:Expression) -> String : match(e) : @@ -92,6 +95,8 @@ defn emit (e:Expression) -> String : LESS-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " <= " emit-signed-if-any(args(e)[1],args(e))] GREATER-OP : [emit-signed-if-any(args(e)[0],args(e)) " > " emit-signed-if-any(args(e)[1],args(e))] GREATER-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " >= " emit-signed-if-any(args(e)[1],args(e))] + NEQUIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))] + EQUIV-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))] NEQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))] EQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))] MUX-OP : @@ -309,11 +314,10 @@ defn emit-module (m:InModule) : println("endmodule") -public defn emit-verilog (file:String, c:Circuit) : - with-output-file{file, _} $ fn () : +public defn emit-verilog (with-output:(() -> False) -> False, c:Circuit) : + with-output $ fn () : for m in modules(c) do : match(m) : (m:InModule) : emit-module(m) (m:ExModule) : false - c diff --git a/test/chisel3/Core.fir b/test/chisel3/Core.fir index 7e87bb07..297f60cb 100644 --- a/test/chisel3/Core.fir +++ b/test/chisel3/Core.fir @@ -10,23 +10,23 @@ circuit Core : input alu_op : UInt<4> node shamt = bits(B, 4, 0) - node T_1224 = add-wrap(A, B) - node T_1225 = sub-wrap(A, B) - node T_1226 = as-SInt(A) + node T_1224 = addw(A, B) + node T_1225 = subw(A, B) + node T_1226 = asSInt(A) node T_1227 = dshr(T_1226, shamt) - node T_1228 = as-UInt(T_1227) + node T_1228 = asUInt(T_1227) node T_1229 = dshr(A, shamt) node T_1230 = dshl(A, shamt) node T_1231 = bits(T_1230, 31, 0) - node T_1232 = as-SInt(A) - node T_1233 = as-SInt(B) + node T_1232 = asSInt(A) + node T_1233 = asSInt(B) node T_1234 = lt(T_1232, T_1233) - node T_1235 = as-UInt(T_1234) + node T_1235 = asUInt(T_1234) node T_1236 = lt(A, B) - node T_1237 = as-UInt(T_1236) - node T_1238 = bit-and(A, B) - node T_1239 = bit-or(A, B) - node T_1240 = bit-xor(A, B) + node T_1237 = asUInt(T_1236) + node T_1238 = and(A, B) + node T_1239 = or(A, B) + node T_1240 = xor(A, B) node T_1241 = eq(UInt<4>(10), alu_op) node T_1242 = mux(T_1241, A, B) node T_1243 = eq(UInt<4>(4), alu_op) @@ -52,9 +52,9 @@ circuit Core : node T_1262 = bits(oot, 31, 0) out := T_1262 node T_1263 = bit(alu_op, 0) - node T_1264 = sub-wrap(UInt<1>(0), B) + node T_1264 = subw(UInt<1>(0), B) node T_1265 = mux(T_1263, T_1264, B) - node T_1266 = add-wrap(A, T_1265) + node T_1266 = addw(A, T_1265) sum := T_1266 module BrCond : input br_type : UInt<3> @@ -63,30 +63,30 @@ circuit Core : output taken : UInt<1> node eq = eq(rs1, rs2) - node neq = bit-not(eq) - node T_1267 = as-SInt(rs1) - node T_1268 = as-SInt(rs2) + node neq = not(eq) + node T_1267 = asSInt(rs1) + node T_1268 = asSInt(rs2) node lt = lt(T_1267, T_1268) - node ge = bit-not(lt) + node ge = not(lt) node ltu = lt(rs1, rs2) - node geu = bit-not(ltu) + node geu = not(ltu) node T_1269 = eq(br_type, UInt<3>(2)) - node T_1270 = bit-and(T_1269, eq) + node T_1270 = and(T_1269, eq) node T_1271 = eq(br_type, UInt<3>(6)) - node T_1272 = bit-and(T_1271, neq) - node T_1273 = bit-or(T_1270, T_1272) + node T_1272 = and(T_1271, neq) + node T_1273 = or(T_1270, T_1272) node T_1274 = eq(br_type, UInt<3>(1)) - node T_1275 = bit-and(T_1274, lt) - node T_1276 = bit-or(T_1273, T_1275) + node T_1275 = and(T_1274, lt) + node T_1276 = or(T_1273, T_1275) node T_1277 = eq(br_type, UInt<3>(5)) - node T_1278 = bit-and(T_1277, ge) - node T_1279 = bit-or(T_1276, T_1278) + node T_1278 = and(T_1277, ge) + node T_1279 = or(T_1276, T_1278) node T_1280 = eq(br_type, UInt<3>(0)) - node T_1281 = bit-and(T_1280, ltu) - node T_1282 = bit-or(T_1279, T_1281) + node T_1281 = and(T_1280, ltu) + node T_1282 = or(T_1279, T_1281) node T_1283 = eq(br_type, UInt<3>(4)) - node T_1284 = bit-and(T_1283, geu) - node T_1285 = bit-or(T_1282, T_1284) + node T_1284 = and(T_1283, geu) + node T_1285 = or(T_1282, T_1284) taken := T_1285 module RegFile : input raddr1 : UInt<5> @@ -96,21 +96,22 @@ circuit Core : input wen : UInt<1> input waddr : UInt<5> input wdata : UInt<32> + input clk : Clock - cmem regs : UInt<32>[32] + cmem regs : UInt<32>[32],clk node T_1286 = eq(raddr1, UInt<1>(0)) - node T_1287 = bit-not(T_1286) + node T_1287 = not(T_1286) infer accessor T_1288 = regs[raddr1] node T_1289 = mux(T_1287, T_1288, UInt<1>(0)) rdata1 := T_1289 node T_1290 = eq(raddr2, UInt<1>(0)) - node T_1291 = bit-not(T_1290) + node T_1291 = not(T_1290) infer accessor T_1292 = regs[raddr2] node T_1293 = mux(T_1291, T_1292, UInt<1>(0)) rdata2 := T_1293 node T_1294 = eq(waddr, UInt<1>(0)) - node T_1295 = bit-not(T_1294) - node T_1296 = bit-and(wen, T_1295) + node T_1295 = not(T_1294) + node T_1296 = and(wen, T_1295) when T_1296 : infer accessor T_1297 = regs[waddr] T_1297 := wdata @@ -120,11 +121,11 @@ circuit Core : input inst : UInt<32> node T_1298 = bits(inst, 31, 20) - node Iimm = as-SInt(T_1298) + node Iimm = asSInt(T_1298) node T_1299 = bits(inst, 31, 25) node T_1300 = bits(inst, 11, 7) node T_1301 = cat(T_1299, T_1300) - node Simm = as-SInt(T_1301) + node Simm = asSInt(T_1301) node T_1302 = bit(inst, 31) node T_1303 = bit(inst, 7) node T_1304 = bits(inst, 30, 25) @@ -133,10 +134,10 @@ circuit Core : node T_1307 = cat(T_1305, UInt<1>(0)) node T_1308 = cat(T_1304, T_1307) node T_1309 = cat(T_1306, T_1308) - node Bimm = as-SInt(T_1309) + node Bimm = asSInt(T_1309) node T_1310 = bits(inst, 31, 12) node T_1311 = cat(T_1310, UInt<12>(0)) - node Uimm = as-SInt(T_1311) + node Uimm = asSInt(T_1311) node T_1312 = bit(inst, 31) node T_1313 = bits(inst, 19, 12) node T_1314 = bit(inst, 20) @@ -147,10 +148,10 @@ circuit Core : node T_1319 = cat(T_1316, UInt<1>(0)) node T_1320 = cat(T_1315, T_1319) node T_1321 = cat(T_1318, T_1320) - node Jimm = as-SInt(T_1321) + node Jimm = asSInt(T_1321) node T_1322 = bits(inst, 19, 15) node T_1323 = pad(T_1322, 32) - node Zimm = as-SInt(T_1323) + node Zimm = asSInt(T_1323) node T_1324 = eq(UInt<3>(3), sel) node T_1325 = mux(T_1324, Jimm, Zimm) node T_1326 = eq(UInt<3>(2), sel) @@ -161,7 +162,7 @@ circuit Core : node T_1331 = mux(T_1330, Simm, T_1329) node T_1332 = eq(UInt<3>(0), sel) node T_1333 = mux(T_1332, Iimm, T_1331) - node T_1334 = as-UInt(T_1333) + node T_1334 = asUInt(T_1333) out := T_1334 module CSR : output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} @@ -169,11 +170,13 @@ circuit Core : input cmd : UInt<2> output data : UInt<32> input addr : UInt<12> + input clk : Clock + input reset : UInt<1> - reg reg_tohost : UInt<32> - on-reset reg_tohost := UInt<32>(0) - reg reg_status : UInt<32> - on-reset reg_status := UInt<32>(0) + reg reg_tohost : UInt<32>,clk,reset + onreset reg_tohost := UInt<32>(0) + reg reg_status : UInt<32>,clk,reset + onreset reg_status := UInt<32>(0) host.tohost := reg_tohost host.status := reg_status node T_1335 = eq(UInt<12>(1291), addr) @@ -191,31 +194,31 @@ circuit Core : when T_1343 : reg_status := src node T_1344 = eq(cmd, UInt<2>(2)) node T_1345 = neq(src, UInt<1>(0)) - node T_1346 = bit-and(T_1344, T_1345) + node T_1346 = and(T_1344, T_1345) when T_1346 : node T_1347 = eq(addr, UInt<12>(1310)) when T_1347 : node T_1348 = dshl(UInt<1>(1), bits(src,5,0)) - node T_1349 = bit-or(data, T_1348) + node T_1349 = or(data, T_1348) reg_tohost := T_1349 node T_1350 = eq(addr, UInt<12>(1290)) when T_1350 : node T_1351 = dshl(UInt<1>(1), bits(src,5,0)) - node T_1352 = bit-or(data, T_1351) + node T_1352 = or(data, T_1351) reg_status := T_1352 node T_1353 = eq(cmd, UInt<2>(3)) node T_1354 = neq(src, UInt<1>(0)) - node T_1355 = bit-and(T_1353, T_1354) + node T_1355 = and(T_1353, T_1354) when T_1355 : node T_1356 = eq(addr, UInt<12>(1310)) when T_1356 : node T_1357 = dshl(UInt<1>(0), bits(src,5,0)) - node T_1358 = bit-and(data, T_1357) + node T_1358 = and(data, T_1357) reg_tohost := T_1358 node T_1359 = eq(addr, UInt<12>(1290)) when T_1359 : node T_1360 = dshl(UInt<1>(0), bits(src,5,0)) - node T_1361 = bit-and(data, T_1360) + node T_1361 = and(data, T_1360) reg_status := T_1361 module Datapath : output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>} @@ -223,39 +226,42 @@ circuit Core : output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} input stall : UInt<1> + input clk : Clock + input reset : UInt<1> inst alu of ALU inst brCond of BrCond inst regFile of RegFile + regFile.clk := clk inst immGen of ImmGenWire - reg fe_inst : UInt<32> - on-reset fe_inst := UInt<32>(0) - reg fe_pc : UInt - reg ew_inst : UInt<32> - on-reset ew_inst := UInt<32>(0) - reg ew_pc : UInt - reg ew_alu : UInt - node T_1362 = sub-wrap(UInt<14>(8192), UInt<32>(4)) - reg pc : UInt<32> - on-reset pc := T_1362 + reg fe_inst : UInt<32>,clk,reset + onreset fe_inst := UInt<32>(0) + reg fe_pc : UInt,clk,reset + reg ew_inst : UInt<32>,clk,reset + onreset ew_inst := UInt<32>(0) + reg ew_pc : UInt,clk,reset + reg ew_alu : UInt,clk,reset + node T_1362 = subw(UInt<14>(8192), UInt<32>(4)) + reg pc : UInt<32>,clk,reset + onreset pc := T_1362 node T_1363 = eq(ctrl.pc_sel, UInt<1>(1)) - node T_1364 = bit-or(T_1363, brCond.taken) - node T_1365 = add-wrap(pc, UInt<3>(4)) + node T_1364 = or(T_1363, brCond.taken) + node T_1365 = addw(pc, UInt<3>(4)) node iaddr = mux(T_1364, alu.sum, T_1365) node T_1366 = eq(ctrl.inst_type, UInt<1>(1)) - node T_1367 = bit-or(T_1366, brCond.taken) + node T_1367 = or(T_1366, brCond.taken) node inst = mux(T_1367, UInt<32>(19), icache.dout) icache.we := UInt<1>(0) icache.din := UInt<1>(0) icache.addr := iaddr icache.re := ctrl.inst_re node T_1368 = eq(dcache.we, UInt<1>(0)) - node T_1369 = bit-not(T_1368) - node T_1370 = bit-not(T_1369) - node T_1371 = bit-and(icache.re, T_1370) + node T_1369 = not(T_1368) + node T_1370 = not(T_1369) + node T_1371 = and(icache.re, T_1370) node T_1372 = mux(T_1371, iaddr, pc) pc := T_1372 - node T_1373 = bit-not(stall) + node T_1373 = not(stall) when T_1373 : fe_pc := pc fe_inst := inst @@ -269,19 +275,19 @@ circuit Core : immGen.inst := fe_inst immGen.sel := ctrl.imm_sel node T_1374 = eq(rs1_addr, UInt<1>(0)) - node rs1NotZero = bit-not(T_1374) + node rs1NotZero = not(T_1374) node T_1375 = eq(rs2_addr, UInt<1>(0)) - node rs2NotZero = bit-not(T_1375) + node rs2NotZero = not(T_1375) node T_1376 = eq(ctrl.wb_sel, UInt<2>(0)) - node alutype = bit-and(ctrl.wb_en, T_1376) + node alutype = and(ctrl.wb_en, T_1376) node ex_rd_addr = bits(ew_inst, 11, 7) - node T_1377 = bit-and(alutype, rs1NotZero) + node T_1377 = and(alutype, rs1NotZero) node T_1378 = eq(rs1_addr, ex_rd_addr) - node T_1379 = bit-and(T_1377, T_1378) + node T_1379 = and(T_1377, T_1378) node rs1 = mux(T_1379, ew_alu, regFile.rdata1) - node T_1380 = bit-and(alutype, rs2NotZero) + node T_1380 = and(alutype, rs2NotZero) node T_1381 = eq(rs2_addr, ex_rd_addr) - node T_1382 = bit-and(T_1380, T_1381) + node T_1382 = and(T_1380, T_1381) node rs2 = mux(T_1382, ew_alu, regFile.rdata2) node T_1383 = eq(ctrl.A_sel, UInt<1>(0)) node T_1384 = mux(T_1383, rs1, fe_pc) @@ -297,7 +303,7 @@ circuit Core : node T_1388 = dshl(T_1387, UInt<3>(4)) node T_1389 = bit(alu.sum, 0) node T_1390 = dshl(T_1389, UInt<2>(3)) - node woffset = bit-or(T_1388, T_1390) + node woffset = or(T_1388, T_1390) dcache.re := ctrl.data_re node T_1391 = mux(stall, ew_alu, alu.sum) dcache.addr := T_1391 @@ -318,7 +324,7 @@ circuit Core : node T_1405 = dshl(rs2, woffset) node T_1406 = bits(T_1405, 31, 0) dcache.din := T_1406 - node T_1407 = bit-not(stall) + node T_1407 = not(stall) when T_1407 : ew_pc := fe_pc ew_inst := fe_inst @@ -327,16 +333,16 @@ circuit Core : node T_1409 = dshl(T_1408, UInt<3>(4)) node T_1410 = bit(ew_alu, 0) node T_1411 = dshl(T_1410, UInt<2>(3)) - node loffset = bit-or(T_1409, T_1411) + node loffset = or(T_1409, T_1411) node lshift = dshr(dcache.dout, loffset) node T_1412 = bits(lshift, 15, 0) - node T_1413 = as-SInt(T_1412) + node T_1413 = asSInt(T_1412) node T_1414 = pad(T_1413, 32) - node T_1415 = as-UInt(T_1414) + node T_1415 = asUInt(T_1414) node T_1416 = bits(lshift, 7, 0) - node T_1417 = as-SInt(T_1416) + node T_1417 = asSInt(T_1416) node T_1418 = pad(T_1417, 32) - node T_1419 = as-UInt(T_1418) + node T_1419 = asUInt(T_1418) node T_1420 = bits(lshift, 15, 0) node T_1421 = bits(lshift, 7, 0) node T_1422 = eq(UInt<3>(4), ctrl.ld_type) @@ -348,12 +354,14 @@ circuit Core : node T_1428 = eq(UInt<3>(1), ctrl.ld_type) node load = mux(T_1428, T_1415, T_1427) inst csr of CSR + csr.clk := clk + csr.reset := reset host := csr.host csr.src := ew_alu node T_1429 = bits(ew_inst, 31, 20) csr.addr := T_1429 csr.cmd := ctrl.csr_cmd - node T_1430 = add-wrap(ew_pc, UInt<3>(4)) + node T_1430 = addw(ew_pc, UInt<3>(4)) node T_1431 = eq(UInt<2>(3), ctrl.wb_sel) node T_1432 = mux(T_1431, csr.data, ew_alu) node T_1433 = eq(UInt<2>(2), ctrl.wb_sel) @@ -364,9 +372,9 @@ circuit Core : regFile.waddr := ex_rd_addr regFile.wdata := regWrite module Control : + output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} input clk : Clock input reset : UInt<1> - output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>} node T_831 = and(UInt<7>(127), ctrl.inst) node T_832 = eq(T_831, UInt<6>(55)) @@ -1015,9 +1023,15 @@ circuit Core : output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>} input stall : UInt<1> + input clk : Clock + input reset : UInt<1> inst dpath of Datapath + dpath.clk := clk + dpath.reset := reset inst ctrl of Control + ctrl.clk := clk + ctrl.reset := reset host := dpath.host icache := dpath.icache dcache := dpath.dcache diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir new file mode 100644 index 00000000..2b1792aa --- /dev/null +++ b/test/errors/gender/BulkWrong.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Expression req is used as a sink but can only be used as a source. + +circuit BTB : + module BTB : + input clk : Clock + input reset : UInt<1> + input req : {valid : UInt<1>, bits : {addr : UInt<39>}} + + wire x : {valid : UInt<1>, bits : {addr : UInt<39>}} + + req <> x diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir index 62eba530..c1a3702a 100644 --- a/test/errors/high-form/Flip-Mem.fir +++ b/test/errors/high-form/Flip-Mem.fir @@ -1,9 +1,9 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s -; CHECK: Memory m-c cannot be a bundle type with flips. -; CHECK: Memory m-s cannot be a bundle type with flips. +; CHECK: Memory mc cannot be a bundle type with flips. +; CHECK: Memory ms cannot be a bundle type with flips. circuit Flip-Mem : module Flip-Mem : input clk : Clock - cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10], clk - smem m-s : {x : UInt<3>, flip y : UInt<5>}[10], clk + cmem mc : {x : UInt<3>, flip y : UInt<5>}[10], clk + smem ms : {x : UInt<3>, flip y : UInt<5>}[10], clk diff --git a/test/errors/high-form/Prefix.fir b/test/errors/high-form/Prefix.fir index 2f0a0247..03908f1c 100644 --- a/test/errors/high-form/Prefix.fir +++ b/test/errors/high-form/Prefix.fir @@ -1,5 +1,6 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Reference x$y and x share a prefix. +; XFAIL: * circuit Top : module Top : diff --git a/test/errors/high-form/RemoveScope.fir b/test/errors/high-form/RemoveScope.fir index 1d9f7ef6..395c6492 100644 --- a/test/errors/high-form/RemoveScope.fir +++ b/test/errors/high-form/RemoveScope.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ; CHECK: Done! circuit Top : diff --git a/test/errors/high-form/SpecialChars.fir b/test/errors/high-form/SpecialChars.fir index f224ce68..99df9143 100644 --- a/test/errors/high-form/SpecialChars.fir +++ b/test/errors/high-form/SpecialChars.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s ; CHECK: Done! circuit Top : diff --git a/test/errors/high-form/Unique.fir b/test/errors/high-form/Unique.fir index 26c4c7da..354454fa 100644 --- a/test/errors/high-form/Unique.fir +++ b/test/errors/high-form/Unique.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * ; CHECK: Reference x does not have a unique name. ; CHECK: Reference p does not have a unique name. diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir index b3a5dbc6..00bb95a6 100644 --- a/test/errors/type/Primop.fir +++ b/test/errors/type/Primop.fir @@ -3,7 +3,7 @@ ; CHECK: Primop add cannot operate on non-ground types. ; CHECK: Primop add cannot operate on non-ground types. ; CHECK: Primop bits requires all arguments to be UInt type. -; CHECK: Primop mux requires argument SInt(1) to be a UInt type. +; CHECK: Primop mux requires argument SInt("h00000001") to be a UInt type. circuit Top : module Top : diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir index b47b14ab..13cdfcf9 100644 --- a/test/features/ExModule.fir +++ b/test/features/ExModule.fir @@ -6,7 +6,7 @@ circuit Top : i.x := UInt(1) i.y := UInt(2) z := i.z - exmodule BlackBox : + extmodule BlackBox : input x : UInt<4> input y : UInt<4> output z : UInt<4> diff --git a/test/features/InitializeVec.fir b/test/features/InitializeVec.fir new file mode 100644 index 00000000..30c59fb9 --- /dev/null +++ b/test/features/InitializeVec.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +;CHECK: Done! +circuit Tst : + module Tst : + output in : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>} + output outs : {valid : UInt<1>, flip ready : UInt<1>, bits : UInt<8>}[4] + + in.ready := UInt<1>(1) + outs[0].valid := UInt<1>(0) + outs[0].bits := UInt<1>(0) + outs[1].valid := UInt<1>(0) + outs[1].bits := UInt<1>(0) + outs[2].valid := UInt<1>(0) + outs[2].bits := UInt<1>(0) + outs[3].valid := UInt<1>(0) + outs[3].bits := UInt<1>(0) + in.ready := UInt<1>(1) + infer accessor out = outs[in.bits] + when out.ready : + out.bits := UInt<7>(99) + out.valid := UInt<1>(1) diff --git a/test/features/Link.fir b/test/features/Link.fir new file mode 100644 index 00000000..190341f2 --- /dev/null +++ b/test/features/Link.fir @@ -0,0 +1,14 @@ +; RUN: firrtl -i %s -m /Users/cusgadmin/code/stanza/firrtl/test/features/Queue.fir -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +;CHECK: Lower To Ground +circuit Top : + module Top : + input clk : Clock + input reset : UInt<1> + output out : UInt<10> + + inst q of Queue + q.clk := clk + q.reset := reset + q.in := UInt(1) + out := q.out + diff --git a/test/features/Queue.fir b/test/features/Queue.fir new file mode 100644 index 00000000..345d2a44 --- /dev/null +++ b/test/features/Queue.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s +; CHECK: Done! +circuit Queue : + module Queue : + input in : UInt<10> + output out : UInt<10> + input clk : Clock + input reset : UInt<1> + + reg r : UInt<10>,clk,reset + r := in + out := r diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir index 660ce77e..d385fcaa 100644 --- a/test/passes/expand-accessors/accessor-mem.fir +++ b/test/passes/expand-accessors/accessor-mem.fir @@ -10,7 +10,7 @@ circuit top : infer accessor a = m[i] ;CHECK: read accessor a = m[i] infer accessor b = a[i] ;CHECK: b := (a[0] a[1])[i] infer accessor c = b[i] ;CHECK: c := (b[0] b[1])[i] - wire j : UInt + wire j : UInt<32> j := c infer accessor x = m[i] ;CHECK: write accessor x = m[i] diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index 38bd6fe5..bc1b6892 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -13,21 +13,21 @@ circuit top : a[0].y := UInt(1) a[1].x := UInt(1) a[1].y := UInt(1) - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := a_0_x + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := a{{[_$]+}}0{{[_$]+}}x ; CHECK: node i!0 = i - ; CHECK: when eq(i!0, UInt(1)) : b_x := a_1_x + ; CHECK: when eqv(i!0, UInt("h00000001")) : b{{[_$]+}}x := a{{[_$]+}}1{{[_$]+}}x ; CHECK: node i!1 = i - ; CHECK: when eq(i!1, UInt(0)) : a_0_y := b_y - ; CHECK: when eq(i!1, UInt(1)) : a_1_y := b_y + ; CHECK: when eqv(i!1, UInt("h00000000")) : a{{[_$]+}}0{{[_$]+}}y := b{{[_$]+}}y + ; CHECK: when eqv(i!1, UInt("h00000001")) : a{{[_$]+}}1{{[_$]+}}y := b{{[_$]+}}y j := b.x b.y := UInt(1) diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index 10da47cf..7e366400 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -4,10 +4,10 @@ circuit top : module top : input clk : Clock input reset : UInt<1> - reg r : { x : UInt, flip y : UInt},clk,reset + reg r : { x : UInt, y : UInt},clk,reset wire a : UInt wire b : UInt - wire w : { x : UInt, flip y : UInt} + wire w : { x : UInt, y : UInt} a := UInt(1) b := UInt(2) @@ -17,11 +17,11 @@ circuit top : r.y := b onreset r := w -; CHECK: when UInt(1) : r$x := mux(reset, w$x, a) -; CHECK: when UInt(1) : r$y := b -; CHECK: a := UInt(1) -; CHECK: b := UInt(2) +; CHECK: r$x := mux(reset, w$x, a) +; CHECK: r$y := mux(reset, w$y, b) +; CHECK: a := UInt("h00000001") +; CHECK: b := UInt("h00000002") ; CHECK: w$x := b -; CHECK: w$y := mux(reset, r$y, a) +; CHECK: w$y := a ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index c81ca485..83f9df6a 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -30,5 +30,5 @@ circuit top : onreset r := y r := b r := z -; CHECK: when UInt(1) : r := mux(reset, mux(q, y, mux(p, x, w)), z) +; CHECK: r := mux(reset, mux(q, y, mux(p, x, w)), z) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/non-ref.fir b/test/passes/expand-whens/non-ref.fir new file mode 100644 index 00000000..762619a7 --- /dev/null +++ b/test/passes/expand-whens/non-ref.fir @@ -0,0 +1,12 @@ +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s + +; CHECK: Expand Whens +circuit top : + module top : + input clk : Clock + input reset : UInt<1> + wire x : UInt<1> + +; CHECK-NOT: wire x : UInt<1> +; CHECK: Finished Expand Whens + diff --git a/test/passes/expand-whens/reg-dwc.fir b/test/passes/expand-whens/reg-dwc.fir index ac0f405b..6d5158cc 100644 --- a/test/passes/expand-whens/reg-dwc.fir +++ b/test/passes/expand-whens/reg-dwc.fir @@ -7,7 +7,7 @@ circuit top : p := UInt(1) reg r : UInt,clk,reset when p : - r := UInt(20) + r := UInt(2) ; CHECK: Expand Whens @@ -15,8 +15,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: when p : r := UInt(20) +; CHECK: p := UInt("h00000001") +; CHECK: when p : r := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-dwoc.fir b/test/passes/expand-whens/reg-dwoc.fir index ab6f4915..3bb9515e 100644 --- a/test/passes/expand-whens/reg-dwoc.fir +++ b/test/passes/expand-whens/reg-dwoc.fir @@ -7,17 +7,17 @@ circuit top : p := UInt(1) reg r : UInt,clk,reset when p : - on-reset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: when p : r := mux(reset, UInt(10), UInt(20)) +; CHECK: reg r : UInt, clk, reset +; CHECK: p := UInt("h00000001") +; CHECK: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdc.fir b/test/passes/expand-whens/reg-wdc.fir index 03f5ade9..bba77902 100644 --- a/test/passes/expand-whens/reg-wdc.fir +++ b/test/passes/expand-whens/reg-wdc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,16 +8,16 @@ circuit top : p := UInt(1) when p : reg r : UInt,clk,reset - r := UInt(20) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: p := UInt(1) -; CHECK: r := UInt(20) +; CHECK: reg r : UInt, clk, reset +; CHECK: p := UInt("h00000001") +; CHECK-NOT: when p : r := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/reg-wdoc.fir b/test/passes/expand-whens/reg-wdoc.fir index 1de6d8f4..954048f2 100644 --- a/test/passes/expand-whens/reg-wdoc.fir +++ b/test/passes/expand-whens/reg-wdoc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,8 +8,8 @@ circuit top : p := UInt(1) when p : reg r : UInt,clk,reset - onreset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens @@ -16,8 +17,8 @@ circuit top : ; CHECK: module top : ; CHECK: wire p : UInt ; CHECK: reg r : UInt, clk, reset -; CHECK: p := UInt(1) -; CHECK: r := mux(reset, UInt(10), UInt(20)) +; CHECK: p := UInt("h00000001") +; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index aec64871..4f02896b 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,15 +8,15 @@ circuit top : p := UInt(1) when p : reg r : UInt, clk, reset - onreset r := UInt(10) - r := UInt(20) + onreset r := UInt(1) + r := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: reg r : UInt -; CHECK: r := mux(reset, UInt(10), UInt(20)) +; CHECK: reg r : UInt, clk, reset +; CHECK-NOT: when p : r := mux(reset, UInt("h00000001"), UInt("h00000002")) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/wacc-wdc.fir b/test/passes/expand-whens/wacc-wdc.fir index 653a3e88..3f88a0d0 100644 --- a/test/passes/expand-whens/wacc-wdc.fir +++ b/test/passes/expand-whens/wacc-wdc.fir @@ -1,4 +1,5 @@ ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s +; XFAIL: * circuit top : module top : input clk : Clock @@ -7,17 +8,17 @@ circuit top : p := UInt(1) when p : write accessor a = m[UInt(3)] - a := UInt(20) + a := UInt(2) ; CHECK: Expand Whens ; CHECK: circuit top : ; CHECK: module top : ; CHECK: wire p : UInt -; CHECK: cmem m : UInt<4>[10] -; CHECK: write accessor a : m[UInt(3)] -; CHECK: p := UInt(1) -; CHECK: when p : a := UInt(20) +; CHECK: cmem m : UInt<4>[10], clk +; CHECK: write accessor a = m[UInt("h00000003")] +; CHECK: p := UInt("h00000001") +; CHECK: when p : a := UInt("h00000002") ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 6309b46f..118734b7 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -20,10 +20,10 @@ circuit top : a[8] := UInt(1) a[9] := UInt(1) node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt> - read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)] + read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")] ; CHECK: Finished Infer Types ; CHECK: Resolve Genders -; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)] +; CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h00000003")] ; CHECK: Finished Resolve Genders diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 735a69c9..0848457b 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -18,7 +18,7 @@ circuit top : output v : UInt<1> reg x : UInt,clk,reset reg y : UInt,clk,reset -; CHECK: reg x : UInt +; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt> onreset x := UInt(0) onreset y := UInt(42) when gt(x, y) : @@ -40,7 +40,7 @@ circuit top : x := a y := b v := eq(v, UInt(0)) - ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt(0))@<t:UInt> + ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt("h00000000"))@<t:UInt> z := x module top : input a : UInt<16> diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index 61656e9c..8e5afb1b 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -87,13 +87,25 @@ circuit top : node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - node vneq = neq(a, b) ;CHECK: node vneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node veq = eq(a, c) ;CHECK: node veq = eq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xeq = eq(a, d) ;CHECK: node xeq = eq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node yeq = eq(c, b) ;CHECK: node yeq = eq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vneq = neq(a, c) ;CHECK: node vneq = neq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xneq = neq(a, d) ;CHECK: node xneq = neq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node yneq = neq(c, b) ;CHECK: node yneq = neq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - node veq = eq(a, b) ;CHECK: node veq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + node vneqv = neqv(a, b) ;CHECK: node vneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wneqv = neqv(a, b) ;CHECK: node wneqv = neqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zneqv = neqv(c, d) ;CHECK: node zneqv = neqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node veqv = eqv(a, b) ;CHECK: node veqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node weqv = eqv(a, b) ;CHECK: node weqv = eqv(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zeqv = eqv(c, d) ;CHECK: node zeqv = eqv(c@<t:SInt>, d@<t:SInt>)@<t:UInt> node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index 4858fafb..19b6ac96 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -8,27 +8,27 @@ circuit top : wire j : UInt<32> wire a : UInt<32>[4] - ; CHECK: wire a_0 : UInt<32> - ; CHECK: wire a_1 : UInt<32> - ; CHECK: wire a_2 : UInt<32> - ; CHECK: wire a_3 : UInt<32> + ; CHECK: wire a{{[_$]+}}0 : UInt<32> + ; CHECK: wire a{{[_$]+}}1 : UInt<32> + ; CHECK: wire a{{[_$]+}}2 : UInt<32> + ; CHECK: wire a{{[_$]+}}3 : UInt<32> infer accessor b = a[i] ; CHECK: wire b : UInt<32> - ; CHECK: b := (a_0 a_1 a_2 a_3)[i] + ; CHECK: b := (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] j := b infer accessor c = a[i] ; CHECK: wire c : UInt<32> - ; CHECK: (a_0 a_1 a_2 a_3)[i] := c + ; CHECK: (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] := c c := j cmem p : UInt<32>[4],clk infer accessor t = p[i] - ; CHECK: accessor t = p[i] + ; CHECK: read accessor t = p[i] j := t infer accessor r = p[i] - ; CHECK: accessor r = p[i] + ; CHECK: write accessor r = p[i] r := j ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index ebf81093..fb1c8320 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -7,23 +7,23 @@ circuit top : wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := (a_0_x a_1_x)[i] - ; CHECK: (a_0_y a_1_y)[i] := b_y + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] + ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y j := b infer accessor c = a[i] - ; CHECK: wire c_x : UInt<32> - ; CHECK: wire c_y : UInt<32> - ; CHECK: (a_0_x a_1_x)[i] := c_x - ; CHECK: c_y := (a_0_y a_1_y)[i] + ; CHECK: wire c{{[_$]+}}x : UInt<32> + ; CHECK: wire c{{[_$]+}}y : UInt<32> + ; CHECK: (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] := c{{[_$]+}}x + ; CHECK: c{{[_$]+}}y := (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] c := j diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 7c11cbc5..83318e10 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -17,34 +17,34 @@ circuit top : ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a_x : UInt<5> -;CHECK: output a_y : SInt<5> -;CHECK: output b_x : UInt<5> -;CHECK: input b_y : SInt<5> +;CHECK: input a{{[_$]+}}x : UInt<5> +;CHECK: output a{{[_$]+}}y : SInt<5> +;CHECK: output b{{[_$]+}}x : UInt<5> +;CHECK: input b{{[_$]+}}y : SInt<5> ;CHECK: module top : -;CHECK: input c_x_0 : UInt<5> -;CHECK: input c_x_1 : UInt<5> -;CHECK: input c_x_2 : UInt<5> -;CHECK: input c_x_3 : UInt<5> -;CHECK: input c_x_4 : UInt<5> -;CHECK: output c_y_x_0 : UInt<5> -;CHECK: output c_y_x_1 : UInt<5> -;CHECK: output c_y_x_2 : UInt<5> -;CHECK: input c_y_y : SInt<5> -;CHECK: wire a_x : UInt<5> -;CHECK: wire a_y : SInt<5> -;CHECK: wire b_x : UInt<5> -;CHECK: wire b_y : SInt<5> -;CHECK: a_x := b_x -;CHECK: b_y := a_y +;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5> +;CHECK: wire a{{[_$]+}}x : UInt<5> +;CHECK: wire a{{[_$]+}}y : SInt<5> +;CHECK: wire b{{[_$]+}}x : UInt<5> +;CHECK: wire b{{[_$]+}}y : SInt<5> +;CHECK: a{{[_$]+}}x := b{{[_$]+}}x +;CHECK: b{{[_$]+}}y := a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a_x := a_x -;CHECK: a_y := i.a_y -;CHECK: b_x := i.b_x -;CHECK: i.b_y := b_y -;CHECK: wire d_0 : UInt<5> -;CHECK: wire d_1 : UInt<5> -;CHECK: wire d_2 : UInt<5> -;CHECK: wire d_3 : UInt<5> -;CHECK: wire d_4 : UInt<5> +;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x +;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y +;CHECK: wire d{{[_$]+}}0 : UInt<5> +;CHECK: wire d{{[_$]+}}1 : UInt<5> +;CHECK: wire d{{[_$]+}}2 : UInt<5> +;CHECK: wire d{{[_$]+}}3 : UInt<5> +;CHECK: wire d{{[_$]+}}4 : UInt<5> ;CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 57c68398..cc8c07e6 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -27,9 +27,9 @@ circuit top : ; CHECK: Lower To Ground -; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m> -; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m> -; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m> -; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m> +; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m> +; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m> +; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m> +; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m> ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 1f38d10e..fa149ffc 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -9,29 +9,29 @@ circuit top : wire k : { x : UInt<32>, y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a_0_x : UInt<32> - ; CHECK: wire a_0_y : UInt<32> - ; CHECK: wire a_1_x : UInt<32> - ; CHECK: wire a_1_y : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> + ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> infer accessor b = a[i] - ; CHECK: wire b_x : UInt<32> - ; CHECK: wire b_y : UInt<32> - ; CHECK: b_x := (a_0_x a_1_x)[i] - ; CHECK: (a_0_y a_1_y)[i] := b_y + ; CHECK: wire b{{[_$]+}}x : UInt<32> + ; CHECK: wire b{{[_$]+}}y : UInt<32> + ; CHECK: b{{[_$]+}}x := (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] + ; CHECK: (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] := b{{[_$]+}}y j := b cmem m : { x : UInt<32>, y : UInt<32> }[2],clk - ; CHECK: cmem m_x : UInt<32>[2] - ; CHECK: cmem m_y : UInt<32>[2] + ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2] + ; CHECK: cmem m{{[_$]+}}y : UInt<32>[2] infer accessor c = m[i] ; MALE - ; CHECK: accessor c_x = m_x[i] - ; CHECK: accessor c_y = m_y[i] + ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i] + ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i] c := k - ; CHECK: c_x := k_x - ; CHECK: c_y := k_y + ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x + ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y ; CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index b045aadc..63519cac 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -9,15 +9,15 @@ input reset : UInt<1> output z : UInt - reg r1 : { x : UInt, flip y : SInt },clk,reset - wire q : { x : UInt, flip y : SInt } + reg r1 : { x : UInt, y : SInt },clk,reset + wire q : { x : UInt, y : SInt } onreset r1 := q - ; CHECK: reg r1_x : UInt - ; CHECK: reg r1_y : SInt - ; CHECK: wire q_x : UInt - ; CHECK: wire q_y : SInt - ; CHECK: onreset r1_x := q_x - ; CHECK: onreset q_y := r1_y + ; CHECK: reg r1{{[_$]+}}x : UInt + ; CHECK: reg r1{{[_$]+}}y : SInt + ; CHECK: wire q{{[_$]+}}x : UInt + ; CHECK: wire q{{[_$]+}}y : SInt + ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x + ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y ; CHECK: Finished Lower To Ground |