diff options
| -rw-r--r-- | src/main/stanza/passes.stanza | 4 | ||||
| -rw-r--r-- | test/passes/to-verilog/escape-quote.fir | 18 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index d0182532..cb4607b8 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -2438,6 +2438,8 @@ defn escape (s:String) -> String : for c in s do : if c == '\n' : add(s*,"\\n") + else if c == '"' : + add(s*, "\\\"") else : if c == 'x' and percent : add(s*,"h") @@ -2694,7 +2696,7 @@ defn emit-verilog (m:InModule) -> Module : defn stop (ret:Int) -> Streamable : ["$fdisplay(32'h80000002,\"" ret "\");$finish;"] defn printf (str:String,args:List<Expression>) -> Streamable : - val str* = join(List(escape(str),args),",") + val str* = join(List(escape(str),map(escape,map(to-string,args))),",") ["$fwrite(32'h80000002," str* ");"] defn delay (e:Expression, n:Int, clk:Expression) -> Expression : var e* = e diff --git a/test/passes/to-verilog/escape-quote.fir b/test/passes/to-verilog/escape-quote.fir new file mode 100644 index 00000000..224026a9 --- /dev/null +++ b/test/passes/to-verilog/escape-quote.fir @@ -0,0 +1,18 @@ +; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s + +;CHECK: module top( +;CHECK: input clk +;CHECK: ); +;CHECK: always @(posedge clk) begin +;CHECK: `ifndef SYNTHESIS +;CHECK: if(1'h1) begin +;CHECK: $fwrite(32'h80000002,"This has an escaped quote (\") in it"); +;CHECK: end +;CHECK: `endif +;CHECK: end +;CHECK: endmodule + +circuit top : + module top : + input clk : Clock + printf(clk, UInt<1>(1), "This has an escaped quote (\") in it") |