diff options
| -rw-r--r-- | src/main/stanza/errors.stanza | 20 | ||||
| -rw-r--r-- | src/main/stanza/primop.stanza | 18 | ||||
| -rw-r--r-- | test/passes/expand-whens/one-when.fir | 40 | ||||
| -rw-r--r-- | test/passes/expand-whens/two-when.fir | 40 | ||||
| -rw-r--r-- | test/passes/infer-types/primops.fir | 2 |
5 files changed, 25 insertions, 95 deletions
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 63199b4b..fb754406 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -517,16 +517,16 @@ defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) - SHIFT-RIGHT-OP : false CONVERT-OP : false NEG-OP : false - BIT-NOT-OP : all-same-type(args(e)) - BIT-AND-OP : all-same-type(args(e)) - BIT-OR-OP : all-same-type(args(e)) - BIT-XOR-OP : all-same-type(args(e)) - BIT-SELECT-OP : false - BITS-SELECT-OP : false - BIT-AND-REDUCE-OP : all-uint(args(e)) - BIT-OR-REDUCE-OP : all-uint(args(e)) - BIT-XOR-REDUCE-OP : all-uint(args(e)) - CONCAT-OP : all-uint(args(e)) + BIT-NOT-OP : all-same-type(args(e)) ;can be either uint or sint + BIT-AND-OP : all-same-type(args(e)) ;can be either uint or sint + BIT-OR-OP : all-same-type(args(e)) ;can be either uint or sint + BIT-XOR-OP : all-same-type(args(e)) ;can be either uint or sint + BIT-SELECT-OP : false ;can be either uint or sint + BITS-SELECT-OP : false ;can be either uint or sint + BIT-AND-REDUCE-OP : false ;can be either uint or sint + BIT-OR-REDUCE-OP : false ;can be either uint or sint + BIT-XOR-REDUCE-OP : false ;can be either uint or sint + CONCAT-OP : false ;can be either uint or sint ;----------------- Check Types Pass --------------------- public defn check-types (c:Circuit) -> Circuit : diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index 6c43c494..2a2d75f2 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -146,9 +146,21 @@ public defn set-primop-type (e:DoPrim) -> DoPrim : (t1:SIntType) : SIntType(w1()) (t1) : UnknownType() BIT-NOT-OP : DoPrim(o,a,c,t1()) - BIT-AND-OP : DoPrim(o,a,c,UIntType(MAX(w1(),w2()))) - BIT-OR-OP : DoPrim(o,a,c,UIntType(MAX(w1(),w2()))) - BIT-XOR-OP : DoPrim(o,a,c,UIntType(MAX(w1(),w2()))) + BIT-AND-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType) : UIntType(MAX(w1(),w2())) + (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1) : UnknownType() + BIT-OR-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType) : UIntType(MAX(w1(),w2())) + (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1) : UnknownType() + BIT-XOR-OP : DoPrim{o,a,c,_} $ + match(t1()) : + (t1:UIntType) : UIntType(MAX(w1(),w2())) + (t1:SIntType) : SIntType(MAX(w1(),w2())) + (t1) : UnknownType() BIT-AND-REDUCE-OP : DoPrim(o,a,c,BoolType()) BIT-OR-REDUCE-OP : DoPrim(o,a,c,BoolType()) BIT-XOR-REDUCE-OP : DoPrim(o,a,c,BoolType()) diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir deleted file mode 100644 index 6eb341d7..00000000 --- a/test/passes/expand-whens/one-when.fir +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - mem m : - data-type => UInt<1> - depth => 2 - read-latency => 0 - write-latency => 1 - wire i : UInt<1> - wire p : UInt<1> - wire j : UInt<1> - j <= UInt(1) - reg r : UInt<1>, clk, reset,i - - p <= j - when p : - - infer accessor a = m[i] - i <= a - infer accessor b = m[i] - b <= i - else : - infer accessor c = m[i] - i <= c - infer accessor d = m[i] - d <= i - infer accessor e = m[i] - when p : - p <= i - when e : - p <= p - r <= p - - -; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir deleted file mode 100644 index 38e02c5e..00000000 --- a/test/passes/expand-whens/two-when.fir +++ /dev/null @@ -1,40 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * - -; CHECK: Expand Whens -circuit top : - module top : - input clk : Clock - cmem m :{ x : UInt<1>, y : UInt<1> }[2], clk - wire i : UInt<1> - i <= UInt(1) - wire p : UInt<1> - p <= UInt(1) - wire q : { x : UInt<1>, y : UInt<1> } - when p : - wire p2 : UInt<1> - p2 <= UInt(1) - when p2 : - infer accessor a = m[i] - q <= a - infer accessor b = m[i] - b <= q - else : - infer accessor c = m[i] - q <= c - infer accessor d = m[i] - d <= q - else : - wire p3 : UInt<1> - p3 <= UInt(1) - when p3 : - infer accessor w = m[i] - q <= w - infer accessor x = m[i] - x <= q - else : - infer accessor y = m[i] - q <= y - infer accessor z = m[i] - z <= q -; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index d2a09367..102a94ae 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -1,6 +1,4 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p ct 2>&1 | tee %s.out | FileCheck %s -; XFAIL: * -; TODO Talk to Andrew about bit operations (and, or, etc.) on SInts ;CHECK: Infer Types circuit top : |