diff options
| -rw-r--r-- | src/main/scala/firrtl/Compiler.scala | 54 | ||||
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 220 |
2 files changed, 137 insertions, 137 deletions
diff --git a/src/main/scala/firrtl/Compiler.scala b/src/main/scala/firrtl/Compiler.scala index 4bc60c00..f566544e 100644 --- a/src/main/scala/firrtl/Compiler.scala +++ b/src/main/scala/firrtl/Compiler.scala @@ -43,7 +43,7 @@ case class RenameMap(map: Map[Named, Seq[Named]]) // Transforms // ------------------------------------------- -case class TransformResult ( +case class TransformResult( circuit: Circuit, renames: Option[RenameMap] = None, annotation: Option[AnnotationMap] = None) @@ -51,7 +51,7 @@ case class TransformResult ( // - Transforms a circuit // - Can consume multiple CircuitAnnotation's trait Transform { - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult } @@ -59,34 +59,36 @@ trait Transform { // Compilers // ------------------------------------------- -case class CompilerResult (circuit: Circuit, annotationMap: AnnotationMap) +case class CompilerResult(circuit: Circuit, annotationMap: AnnotationMap) // - A sequence of transformations // - Call compile to executes each transformation in sequence onto // a given circuit. trait Compiler { - def transforms(w: Writer): Seq[Transform] - def compile(circuit: Circuit, annotationMap: AnnotationMap, writer: Writer): CompilerResult = { - transforms(writer).foldLeft(CompilerResult(circuit,annotationMap))((in: CompilerResult, xform: Transform) => { - val result = xform.execute(in.circuit,in.annotationMap) - val remappedAnnotations: Seq[Annotation] = result.renames match { - case Some(RenameMap(rmap)) => { - // For each key in the rename map (rmap), obtain the - // corresponding annotations (in.annotationMap.get(from)). If any - // annotations exist, for each annotation, create a sequence of - // annotations with the names in rmap's value. - for{ - (oldName, newNames) <- rmap.toSeq - tID2OldAnnos <- in.annotationMap.get(oldName).toSeq - oldAnno <- tID2OldAnnos.values - newAnno <- oldAnno.update(newNames) - } yield newAnno - } - case _ => in.annotationMap.annotations - } - val full_annotations = new AnnotationMap((remappedAnnotations ++ result.annotation.getOrElse(new AnnotationMap(Seq.empty)).annotations).toSeq) - CompilerResult(result.circuit, full_annotations) - }) - } + def transforms(w: Writer): Seq[Transform] + def compile(circuit: Circuit, annotationMap: AnnotationMap, writer: Writer): CompilerResult = + (transforms(writer) foldLeft CompilerResult(circuit, annotationMap)){ (in, xform) => + val result = xform.execute(in.circuit, in.annotationMap) + val remappedAnnotations: Seq[Annotation] = result.renames match { + case Some(RenameMap(rmap)) => + // For each key in the rename map (rmap), obtain the + // corresponding annotations (in.annotationMap.get(from)). If any + // annotations exist, for each annotation, create a sequence of + // annotations with the names in rmap's value. + for { + (oldName, newNames) <- rmap.toSeq + tID2OldAnnos <- in.annotationMap.get(oldName).toSeq + oldAnno <- tID2OldAnnos.values + newAnno <- oldAnno.update(newNames) + } yield newAnno + case _ => in.annotationMap.annotations + } + val resultAnnotations: Seq[Annotation] = result.annotation match { + case None => Nil + case Some(p) => p.annotations + } + CompilerResult(result.circuit, + new AnnotationMap(remappedAnnotations ++ resultAnnotations)) + } } diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 4d40d9a8..cd77fa3e 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -41,17 +41,15 @@ import Annotations._ // 2) Don't consume annotations // 3) No component or module names are renamed trait SimpleRun extends LazyLogging { - def run (circuit: Circuit, passes: Seq[Pass]): TransformResult = { - val result = passes.foldLeft(circuit) { - (c: Circuit, pass: Pass) => { - val name = pass.name - val x = Utils.time(name) { pass.run(c) } - logger.debug(x.serialize) - x - } - } - TransformResult(result) - } + def run (circuit: Circuit, passes: Seq[Pass]): TransformResult = { + val result = (passes foldLeft circuit){ (c: Circuit, pass: Pass) => + val name = pass.name + val x = Utils.time(name)(pass.run(c)) + logger.debug(x.serialize) + x + } + TransformResult(result) + } } // =========================================== @@ -60,77 +58,77 @@ trait SimpleRun extends LazyLogging { // This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting // circuit has only IR nodes, not WIR. // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL -class Chisel3ToHighFirrtl () extends Transform with SimpleRun { - val passSeq = Seq( - passes.CheckChirrtl, - passes.CInferTypes, - passes.CInferMDir, - passes.RemoveCHIRRTL) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +class Chisel3ToHighFirrtl extends Transform with SimpleRun { + val passSeq = Seq( + passes.CheckChirrtl, + passes.CInferTypes, + passes.CInferMDir, + passes.RemoveCHIRRTL) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = + run(circuit, passSeq) } // Converts from the bare intermediate representation (ir.scala) // to a working representation (WIR.scala) -class IRToWorkingIR () extends Transform with SimpleRun { - val passSeq = Seq(passes.ToWorkingIR) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +class IRToWorkingIR extends Transform with SimpleRun { + val passSeq = Seq(passes.ToWorkingIR) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = + run(circuit, passSeq) } // Resolves types, kinds, and genders, and checks the circuit legality. // Operates on working IR nodes and high Firrtl. -class ResolveAndCheck () extends Transform with SimpleRun { - val passSeq = Seq( - passes.CheckHighForm, - passes.ResolveKinds, - passes.InferTypes, - passes.CheckTypes, - passes.Uniquify, - passes.ResolveKinds, - passes.InferTypes, - passes.ResolveGenders, - passes.CheckGenders, - passes.InferWidths, - passes.CheckWidths) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +class ResolveAndCheck extends Transform with SimpleRun { + val passSeq = Seq( + passes.CheckHighForm, + passes.ResolveKinds, + passes.InferTypes, + passes.CheckTypes, + passes.Uniquify, + passes.ResolveKinds, + passes.InferTypes, + passes.ResolveGenders, + passes.CheckGenders, + passes.InferWidths, + passes.CheckWidths) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = + run(circuit, passSeq) } // Expands aggregate connects, removes dynamic accesses, and when // statements. Checks for uninitialized values. Must accept a // well-formed graph. // Operates on working IR nodes. -class HighFirrtlToMiddleFirrtl () extends Transform with SimpleRun { - val passSeq = Seq( - passes.PullMuxes, - passes.ReplaceAccesses, - passes.ExpandConnects, - passes.RemoveAccesses, - passes.ExpandWhens, - passes.CheckInitialization, - passes.ResolveKinds, - passes.InferTypes, - passes.ResolveGenders, - passes.InferWidths, - passes.CheckWidths) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +class HighFirrtlToMiddleFirrtl extends Transform with SimpleRun { + val passSeq = Seq( + passes.PullMuxes, + passes.ReplaceAccesses, + passes.ExpandConnects, + passes.RemoveAccesses, + passes.ExpandWhens, + passes.CheckInitialization, + passes.ResolveKinds, + passes.InferTypes, + passes.ResolveGenders, + passes.InferWidths, + passes.CheckWidths) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = + run(circuit, passSeq) } // Expands all aggregate types into many ground-typed components. Must // accept a well-formed graph of only middle Firrtl features. // Operates on working IR nodes. // TODO(izraelevitz): Create RenameMap from RemoveCHIRRTL -class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun { - val passSeq = Seq( - passes.LowerTypes, - passes.ResolveKinds, - passes.InferTypes, - passes.ResolveGenders, - passes.InferWidths) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = - run(circuit, passSeq) +class MiddleFirrtlToLowFirrtl extends Transform with SimpleRun { + val passSeq = Seq( + passes.LowerTypes, + passes.ResolveKinds, + passes.InferTypes, + passes.ResolveGenders, + passes.InferWidths) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = + run(circuit, passSeq) } // Emits Verilog. @@ -139,32 +137,32 @@ class MiddleFirrtlToLowFirrtl () extends Transform with SimpleRun { // renames names that conflict with Verilog keywords. // Operates on working IR nodes. // TODO(izraelevitz): Create RenameMap from VerilogRename -class EmitVerilogFromLowFirrtl (val writer: Writer) extends Transform with SimpleRun { - val passSeq = Seq( - passes.RemoveValidIf, - passes.ConstProp, - passes.PadWidths, - passes.ConstProp, - passes.Legalize, - passes.VerilogWrap, - passes.SplitExpressions, - passes.CommonSubexpressionElimination, - passes.DeadCodeElimination, - passes.VerilogRename) - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { - val result = run(circuit, passSeq) - (new VerilogEmitter).run(result.circuit, writer) - result - } +class EmitVerilogFromLowFirrtl(val writer: Writer) extends Transform with SimpleRun { + val passSeq = Seq( + passes.RemoveValidIf, + passes.ConstProp, + passes.PadWidths, + passes.ConstProp, + passes.Legalize, + passes.VerilogWrap, + passes.SplitExpressions, + passes.CommonSubexpressionElimination, + passes.DeadCodeElimination, + passes.VerilogRename) + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { + val result = run(circuit, passSeq) + (new VerilogEmitter).run(result.circuit, writer) + result + } } // Emits Firrtl. // Operates on WIR/IR nodes. -class EmitFirrtl (val writer: Writer) extends Transform { - def execute (circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { - FIRRTLEmitter.run(circuit, writer) - TransformResult(circuit) - } +class EmitFirrtl(val writer: Writer) extends Transform { + def execute(circuit: Circuit, annotationMap: AnnotationMap): TransformResult = { + FIRRTLEmitter.run(circuit, writer) + TransformResult(circuit) + } } @@ -174,39 +172,39 @@ class EmitFirrtl (val writer: Writer) extends Transform { // Emits input circuit // Will replace Chirrtl constructs with Firrtl class HighFirrtlCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl(), - new IRToWorkingIR(), - new EmitFirrtl(writer) - ) + def transforms(writer: Writer): Seq[Transform] = Seq( + new Chisel3ToHighFirrtl, + new IRToWorkingIR, + new EmitFirrtl(writer) + ) } // Emits lowered input circuit class LowFirrtlCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl(), - new IRToWorkingIR(), - new passes.InlineInstances(TransID(0)), - new ResolveAndCheck(), - new HighFirrtlToMiddleFirrtl(), - new passes.InferReadWrite(TransID(-1)), - new passes.ReplSeqMem(TransID(-2)), - new MiddleFirrtlToLowFirrtl(), - new EmitFirrtl(writer) - ) + def transforms(writer: Writer): Seq[Transform] = Seq( + new Chisel3ToHighFirrtl, + new IRToWorkingIR, + new passes.InlineInstances(TransID(0)), + new ResolveAndCheck, + new HighFirrtlToMiddleFirrtl, + new passes.InferReadWrite(TransID(-1)), + new passes.ReplSeqMem(TransID(-2)), + new MiddleFirrtlToLowFirrtl, + new EmitFirrtl(writer) + ) } // Emits Verilog class VerilogCompiler extends Compiler { - def transforms(writer: Writer): Seq[Transform] = Seq( - new Chisel3ToHighFirrtl(), - new IRToWorkingIR(), - new ResolveAndCheck(), - new HighFirrtlToMiddleFirrtl(), - new passes.InferReadWrite(TransID(-1)), - new passes.ReplSeqMem(TransID(-2)), - new MiddleFirrtlToLowFirrtl(), - new passes.InlineInstances(TransID(0)), - new EmitVerilogFromLowFirrtl(writer) - ) + def transforms(writer: Writer): Seq[Transform] = Seq( + new Chisel3ToHighFirrtl, + new IRToWorkingIR, + new ResolveAndCheck, + new HighFirrtlToMiddleFirrtl, + new passes.InferReadWrite(TransID(-1)), + new passes.ReplSeqMem(TransID(-2)), + new MiddleFirrtlToLowFirrtl, + new passes.InlineInstances(TransID(0)), + new EmitVerilogFromLowFirrtl(writer) + ) } |