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authorazidar2015-03-25 21:05:18 -0700
committerazidar2015-03-25 21:05:18 -0700
commita1a1156df859eb815f8b345d24198dbfe3857832 (patch)
tree701f4e9677b4f488f4d073656f8368bc1e0e626e /test
parent612132bf95b529d2fafbe96e622f716ca9514679 (diff)
Finished expand-whens. Removed letrec also, a while ago
Diffstat (limited to 'test')
-rw-r--r--test/passes/expand-whens/one-when.fir1
-rw-r--r--test/passes/lower-to-ground/accessor.fir6
2 files changed, 4 insertions, 3 deletions
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 66fc2ef6..49fe7757 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -27,6 +27,7 @@ circuit top :
when e :
p := p
r.init := p
+ r := p
; CHECK: Finished Expand Whens
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 56171246..e54868bc 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -3,8 +3,8 @@
; CHECK: Lower To Ground
circuit top :
module m :
- wire i : UInt
- wire j : UInt
+ wire i : UInt(2)
+ wire j : UInt(32)
wire a : UInt(32)[4]
; CHECK: wire a#0 : UInt(32)
@@ -22,7 +22,7 @@ circuit top :
; CHECK: (a#0 a#1 a#2 a#3)[i] := c
c := j
- mem p : UInt(32)[10]
+ mem p : UInt(32)[4]
accessor t = p[i]
; CHECK: accessor t = p[i]
j := t