Finished expand accessors and lower to ground

10 files changed, 214 insertions, 89 deletions

diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 32002d47..01257279 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -5,15 +5,15 @@ circuit top :
    module top :
       mem m : UInt(32)[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: a := ReadPort(m, i, UInt(1))
-      accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
-      accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+      accessor a = m[i] ;CHECK: accessor a = m[i]
+      accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
+      accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: WritePort(m, i, UInt(1)) := x
-      accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
-      accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+      accessor x = m[i] ;CHECK: accessor x = m[i]
+      accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
+      accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
       z := j
 
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/accessor-vec.fir b/test/passes/expand-accessors/accessor-vec.fir
index 4314e062..599abb8f 100644
--- a/test/passes/expand-accessors/accessor-vec.fir
+++ b/test/passes/expand-accessors/accessor-vec.fir
@@ -5,15 +5,23 @@ circuit top :
    module top :
       wire m : UInt(32)[10][10][10]
       wire i : UInt
-      accessor a = m[i] ;CHECK: a := (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i]
-      accessor b = a[i] ;CHECK: b := (a.9 a.8 a.7 a.6 a.5 a.4 a.3 a.2 a.1 a.0)[i]
-      accessor c = b[i] ;CHECK: c := (b.9 b.8 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0)[i]
+      accessor a = m[i] ;CHECK: a := (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i]
+      accessor b = a[i] ;CHECK: b := (a.0 a.1 a.2 a.3 a.4 a.5 a.6 a.7 a.8 a.9)[i]
+      accessor c = b[i] ;CHECK: c := (b.0 b.1 b.2 b.3 b.4 b.5 b.6 b.7 b.8 b.9)[i]
       wire j : UInt
       j := c
 
-      accessor x = m[i] ;CHECK: (m.9 m.8 m.7 m.6 m.5 m.4 m.3 m.2 m.1 m.0)[i] := x
-      accessor y = x[i] ;CHECK: (x.9 x.8 x.7 x.6 x.5 x.4 x.3 x.2 x.1 x.0)[i] := y
-      accessor z = y[i] ;CHECK: (y.9 y.8 y.7 y.6 y.5 y.4 y.3 y.2 y.1 y.0)[i] := z
+      accessor x = m[i] ;CHECK: (m.0 m.1 m.2 m.3 m.4 m.5 m.6 m.7 m.8 m.9)[i] := x
+      accessor y = x[i] ;CHECK: (x.0 x.1 x.2 x.3 x.4 x.5 x.6 x.7 x.8 x.9)[i] := y
+      accessor z = y[i] ;CHECK: (y.0 y.1 y.2 y.3 y.4 y.5 y.6 y.7 y.8 y.9)[i] := z
       z := j
 
+      wire p : {n : UInt(32)[10]}
+      accessor q = p.n[i] ;CHECK: (p.n.0 p.n.1 p.n.2 p.n.3 p.n.4 p.n.5 p.n.6 p.n.7 p.n.8 p.n.9)[i] := q
+      q := j
+
+      wire r : {m : UInt(32)}[10]
+      accessor s = r[i] ;CHECK: s := (r.0 r.1 r.2 r.3 r.4 r.5 r.6 r.7 r.8 r.9)[i]
+      j := s.m
+
 ; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/one-when.fir b/test/passes/expand-accessors/one-when.fir
deleted file mode 100644
index 2597c1d7..00000000
--- a/test/passes/expand-accessors/one-when.fir
+++ /dev/null
@@ -1,20 +0,0 @@
-; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
-
-;CHECK: Expand Accessors
-circuit top :
-   module top :
-      mem m : UInt(1)[2]
-      wire i : UInt(1)
-      wire p : UInt(1)
-      when p :
-        accessor a = m[i] ;CHECK: a := ReadPort(m, i, bit-and(p, UInt(1)))
-        i := a
-        accessor b = m[i] ;CHECK: WritePort(m, i, bit-and(p, UInt(1))) := b
-        b := i
-      else :
-        accessor c = m[i] ;CHECK: c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1)))
-        i := c
-        accessor d = m[i] ;CHECK: WritePort(m, i, bit-and(equal-uu(UInt(0), p), UInt(1))) := d
-        d := i
-
-; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-accessors/two-when.fir b/test/passes/expand-accessors/two-when.fir
deleted file mode 100644
index 87c8fc54..00000000
--- a/test/passes/expand-accessors/two-when.fir
+++ /dev/null
@@ -1,57 +0,0 @@
-; RUN: firrtl %s abcdefg c | tee %s.out | FileCheck %s
-
-;CHECK: Expand Accessors
-circuit top :
-   module top :
-      mem m : UInt(1)[2]
-      wire i : UInt(1)
-      wire p : UInt(1)
-      when p :
-        wire p2 : UInt(1)
-        when p2 :
-          accessor a = m[i] 
-          i := a
-          accessor b = m[i]
-          b := i
-            ;CHECK : wire a : UInt(1)
-            ;CHECK : a := ReadPort(m, i, bit-and(p2, bit-and(p, UInt(1))))
-            ;CHECK : i := a
-            ;CHECK : wire b : UInt(1)
-            ;CHECK : WritePort(m, i, bit-and(p2, bit-and(p, UInt(1)))) := b
-            ;CHECK : b := i
-        else :
-          accessor c = m[i] 
-          i := c
-          accessor d = m[i]
-          d := i
-            ;CHECK : wire c : UInt(1)
-            ;CHECK : c := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1))))
-            ;CHECK : i := c
-            ;CHECK : wire d : UInt(1)
-            ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(p, UInt(1)))) := d
-            ;CHECK : d := i
-      else :
-        when p2 :
-          accessor w = m[i] 
-          i := w
-          accessor x = m[i]
-          x := i
-            ;CHECK : wire w : UInt(1)
-            ;CHECK : w := ReadPort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1))))
-            ;CHECK : i := w
-            ;CHECK : wire x : UInt(1)
-            ;CHECK : WritePort(m, i, bit-and(p2, bit-and(equal-uu(UInt(0), p), UInt(1)))) := x
-            ;CHECK : x := i
-        else :
-          accessor y = m[i] 
-          i := y
-          accessor z = m[i]
-          z := i
-            ;CHECK : wire y : UInt(1)
-            ;CHECK : y := ReadPort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1))))
-            ;CHECK : i := y
-            ;CHECK : wire z : UInt(1)
-            ;CHECK : WritePort(m, i, bit-and(equal-uu(UInt(0), p2), bit-and(equal-uu(UInt(0), p), UInt(1)))) := z
-            ;CHECK : z := i
-
-; CHECK: Finished Expand Accessors
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
new file mode 100644
index 00000000..78c59493
--- /dev/null
+++ b/test/passes/expand-whens/one-when.fir
@@ -0,0 +1,15 @@
+circuit top :
+   module top :
+      mem m : UInt(1)[2]
+      wire i : UInt(1)
+      wire p : UInt(1)
+      when p :
+        accessor a = m[i] 
+        i := a
+        accessor b = m[i]
+        b := i
+      else :
+        accessor c = m[i]
+        i := c
+        accessor d = m[i] 
+        d := i
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
new file mode 100644
index 00000000..16fae1e2
--- /dev/null
+++ b/test/passes/expand-whens/two-when.fir
@@ -0,0 +1,28 @@
+circuit top :
+   module top :
+      mem m : UInt(1)[2]
+      wire i : UInt(1)
+      wire p : UInt(1)
+      when p :
+        wire p2 : UInt(1)
+        when p2 :
+          accessor a = m[i] 
+          i := a
+          accessor b = m[i]
+          b := i
+        else :
+          accessor c = m[i] 
+          i := c
+          accessor d = m[i]
+          d := i
+      else :
+        when p2 :
+          accessor w = m[i] 
+          i := w
+          accessor x = m[i]
+          x := i
+        else :
+          accessor y = m[i] 
+          i := y
+          accessor z = m[i]
+          z := i
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
new file mode 100644
index 00000000..56171246
--- /dev/null
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -0,0 +1,33 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module m :
+      wire i : UInt
+      wire j : UInt
+
+      wire a : UInt(32)[4]
+      ; CHECK: wire a#0 : UInt(32)
+      ; CHECK: wire a#1 : UInt(32)
+      ; CHECK: wire a#2 : UInt(32)
+      ; CHECK: wire a#3 : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b : UInt(32)
+      ; CHECK: b := (a#0 a#1 a#2 a#3)[i]
+      j := b
+
+      accessor c = a[i]
+      ; CHECK: wire c : UInt(32)
+      ; CHECK: (a#0 a#1 a#2 a#3)[i] := c
+      c := j
+      
+      mem p : UInt(32)[10]
+      accessor t = p[i]
+      ; CHECK: accessor t = p[i]
+      j := t
+      accessor r = p[i]
+      ; CHECK: accessor r = p[i]
+      r := j
+
+; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
new file mode 100644
index 00000000..a4ead6ed
--- /dev/null
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module q :
+      wire i : UInt
+      wire j : UInt
+
+      wire a : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: wire a#0#x : UInt(32)
+      ; CHECK: wire a#0#y : UInt(32)
+      ; CHECK: wire a#1#x : UInt(32)
+      ; CHECK: wire a#1#y : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b#x : UInt(32)
+      ; CHECK: wire b#y : UInt(32)
+      ; CHECK: b#x := (a#0#x a#1#x)[i]
+      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      j := b
+      
+      accessor c = a[i]
+      ; CHECK: wire c#x : UInt(32)
+      ; CHECK: wire c#y : UInt(32)
+      ; CHECK: (a#0#x a#1#x)[i] := c#x
+      ; CHECK: c#y := (a#0#y a#1#y)[i]
+      c := j
+
+
+; CHECK: Finished Lower To Ground
+
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
new file mode 100644
index 00000000..990b6b7f
--- /dev/null
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -0,0 +1,53 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+circuit top :
+   module m :
+      input  a : { x : UInt, flip y: SInt}
+      output b : { x : UInt, flip y: SInt}
+   module subtracter :
+      input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } }
+      wire a : { x : UInt, flip y : SInt}
+      wire b : { x : UInt, flip y : SInt}
+      a := b
+      inst i of m
+      i.a := a
+      b := i.b
+      wire d : UInt[5]
+
+;CHECK: Lower To Ground
+;CHECK: circuit top :
+;CHECK:    module m :
+;CHECK:       input a#x : UInt
+;CHECK:       output a#y : SInt
+;CHECK:       output b#x : UInt
+;CHECK:       input b#y : SInt
+;CHECK:       input reset : UInt(1)
+;CHECK:    module subtracter :
+;CHECK:       input c#x#0 : UInt
+;CHECK:       input c#x#1 : UInt
+;CHECK:       input c#x#2 : UInt
+;CHECK:       input c#x#3 : UInt
+;CHECK:       input c#x#4 : UInt
+;CHECK:       output c#y#x#0 : UInt
+;CHECK:       output c#y#x#1 : UInt
+;CHECK:       output c#y#x#2 : UInt
+;CHECK:       input c#y#y : SInt
+;CHECK:       input reset : UInt(1)
+;CHECK:       wire a#x : UInt
+;CHECK:       wire a#y : SInt
+;CHECK:       wire b#x : UInt
+;CHECK:       wire b#y : SInt
+;CHECK:       a#x := b#x
+;CHECK:       b#y := a#y
+;CHECK:       inst i of m
+;CHECK:       i.reset := reset
+;CHECK:       i.a#x := a#x
+;CHECK:       a#y := i.a#y
+;CHECK:       b#x := i.b#x
+;CHECK:       i.b#y := b#y
+;CHECK:       wire d#0 : UInt
+;CHECK:       wire d#1 : UInt
+;CHECK:       wire d#2 : UInt
+;CHECK:       wire d#3 : UInt
+;CHECK:       wire d#4 : UInt
+;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
new file mode 100644
index 00000000..8eafb8e8
--- /dev/null
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -0,0 +1,34 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module q :
+      wire i : UInt
+      wire j : { x : UInt(32), flip y : UInt(32) }
+
+      wire a : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: wire a#0#x : UInt(32)
+      ; CHECK: wire a#0#y : UInt(32)
+      ; CHECK: wire a#1#x : UInt(32)
+      ; CHECK: wire a#1#y : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b#x : UInt(32)
+      ; CHECK: wire b#y : UInt(32)
+      ; CHECK: b#x := (a#0#x a#1#x)[i]
+      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      j := b
+
+      mem m : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: mem m#x : UInt(32)[2]
+      ; CHECK: mem m#y : UInt(32)[2]
+
+      accessor c = m[i] ; MALE
+      ; CHECK: accessor c#x = m#x[i]
+      ; CHECK: accessor c#y = m#y[i]
+      ; CHECK: c#x := j#x
+      ; CHECK: j#y := c#y
+      c := j
+
+; CHECK: Finished Lower To Ground
+