diff options
| author | jackkoenig | 2016-01-27 11:28:37 -0800 |
|---|---|---|
| committer | jackkoenig | 2016-01-27 11:28:37 -0800 |
| commit | e261bdc2f179a5cb332fa6cc6bb982b54266f866 (patch) | |
| tree | 282086b6fc331f1c073eeeb2e6f2c98334ce7ba2 /test/passes/to-verilog/wr-mem.fir | |
| parent | 1bb91b3af9c6ada9a26c201d163f1338ff7f2be6 (diff) | |
Fixed additional tests and inferring rdwr ports in chirrtl
Diffstat (limited to 'test/passes/to-verilog/wr-mem.fir')
| -rw-r--r-- | test/passes/to-verilog/wr-mem.fir | 40 |
1 files changed, 27 insertions, 13 deletions
diff --git a/test/passes/to-verilog/wr-mem.fir b/test/passes/to-verilog/wr-mem.fir index b21491aa..06745812 100644 --- a/test/passes/to-verilog/wr-mem.fir +++ b/test/passes/to-verilog/wr-mem.fir @@ -7,30 +7,44 @@ circuit top : input wen : UInt<1> input clk : Clock - smem m : UInt<32>[4],clk - write accessor c = m[index] + smem m : UInt<32>[4] + write mport c = m[index],clk when wen : c <= wdata ; CHECK: module top( -; CHECK: input [31:0] wdata, -; CHECK: input [1:0] index, -; CHECK: input [0:0] wen, -; CHECK: input [0:0] clk +; CHECK: input [31:0] wdata, +; CHECK: input [1:0] index, +; CHECK: input wen, +; CHECK: input clk ; CHECK: ); -; CHECK: reg [31:0] m [0:3]; +; CHECK: reg [31:0] m [0:3]; +; CHECK: wire [31:0] m_c_data; +; CHECK: wire [1:0] m_c_addr; +; CHECK: wire m_c_mask; +; CHECK: wire m_c_en; +; CHECK: wire m_c_clk; +; CHECK: reg [1:0] GEN_0; +; CHECK: reg [31:0] GEN_1; +; CHECK: assign m_c_data = wen ? wdata : GEN_1; +; CHECK: assign m_c_addr = index; +; CHECK: assign m_c_mask = wen ? 1'h1 : 1'h0; +; CHECK: assign m_c_en = 1'h1; +; CHECK: assign m_c_clk = clk; ; CHECK: `ifndef SYNTHESIS ; CHECK: integer initvar; ; CHECK: initial begin ; CHECK: #0.002; -; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) +; CHECK: for (initvar = 0; initvar < 4; initvar = initvar+1) ; CHECK: m[initvar] = {1{$random}}; +; CHECK: GEN_0 = {1{$random}}; +; CHECK: GEN_1 = {1{$random}}; ; CHECK: end ; CHECK: `endif -; CHECK: always @(posedge clk) begin -; CHECK: if(wen) begin -; CHECK: m[index] <= wdata; -; CHECK: end -; CHECK: end +; CHECK: always @(posedge m_c_clk) begin +; CHECK: if(m_c_en & m_c_mask) begin +; CHECK: m[m_c_addr] <= m_c_data; +; CHECK: end +; CHECK: end ; CHECK: endmodule |