diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/split-exp | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/split-exp')
| -rw-r--r-- | test/passes/split-exp/gcd.fir | 6 | ||||
| -rw-r--r-- | test/passes/split-exp/primop.fir | 3 | ||||
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 15 |
3 files changed, 12 insertions, 12 deletions
diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 1f032c04..e651f41a 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -14,10 +14,8 @@ circuit top : input b : UInt<16> input e : UInt<1> output z : UInt<16> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) when gt(x, y) : inst s of subtracter s.x <= x diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir index caccf57b..cdbd4e77 100644 --- a/test/passes/split-exp/primop.fir +++ b/test/passes/split-exp/primop.fir @@ -12,7 +12,8 @@ circuit Top : wire x : UInt<1> x <= not(UInt(1)) - infer accessor a = m[x] + wire a : UInt<1> + a <= m[x] out <= a diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index b72a1d95..a6d0a2c5 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -9,15 +9,16 @@ circuit Top : input b : UInt<10> input c : UInt<10> - reg out : UInt<10>,clk,p + reg out : UInt<10>,clk,p,a when bit(subw(a,c),3) : out <= mux(eqv(bits(UInt(32),4,0),UInt(13)),addw(a,addw(b,c)),subw(c,b)) -;CHECK: node F = subw(a, c) -;CHECK: node out_1 = eqv(UInt("h0"), UInt("hd")) -;CHECK: node out_3 = addw(b, c) -;CHECK: node out_2 = addw(a, out_3) -;CHECK: node out_4 = subw(c, b) -;CHECK: when bit(F, 3) : out <= mux(out_1, out_2, out_4) +;CHECK: node out_1 = subw(a, c) +;CHECK: node out_2 = bit(out_1, 3) +;CHECK: node out_3 = eqv(UInt("h0"), UInt("hd")) +;CHECK: node out_4 = addw(b, c) +;CHECK: node out_5 = addw(a, out_4) +;CHECK: node out_6 = subw(c, b) +;CHECK: node out_7 = mux(out_3, out_5, out_6) ;CHECK: Finished Split Expressions |