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| author | azidar | 2016-01-16 15:24:50 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 15:24:50 -0800 |
| commit | 9dcb5684957e684174d97a45f80d1cfad887a741 (patch) | |
| tree | 1c8b53f66bb59cc39d2931910459470f0495c71a /test/passes/split-exp | |
| parent | ed20e7c6c77543756e1ebc7bc1e6ae7d10911f0a (diff) | |
| parent | c4271d9e428bba7b447ed6d18fb11729d2b61b22 (diff) | |
Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem
Diffstat (limited to 'test/passes/split-exp')
| -rw-r--r-- | test/passes/split-exp/split-in-when.fir | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/test/passes/split-exp/split-in-when.fir b/test/passes/split-exp/split-in-when.fir index 06a3cc53..69e2b96e 100644 --- a/test/passes/split-exp/split-in-when.fir +++ b/test/passes/split-exp/split-in-when.fir @@ -19,7 +19,6 @@ circuit Top : ;CHECK: node GEN_3 = addw(b, c) ;CHECK: node GEN_4 = addw(a, GEN_3) ;CHECK: node GEN_5 = subw(c, b) -;CHECK: node GEN_6 = mux(GEN_2, GEN_4, GEN_5) -;CHECK: out <= mux(GEN_1, GEN_6, out) +;CHECK: out <= mux(GEN_1, mux(GEN_2, GEN_4, GEN_5), out) ;CHECK: Finished Split Expressions |