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| author | azidar | 2016-01-28 12:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 12:12:02 -0800 |
| commit | 9ed79a822f7f406c55af8082da04cb7739e772eb (patch) | |
| tree | 02b10696dd0a03faf54c8eafa046855ccfc26e8f /test/passes/split-exp/split-and.fir | |
| parent | b7dcc8ccbb1459a604353a8137081a9b156d276e (diff) | |
| parent | 094c6b8e7b40a3c613547d6127b449d0b1503db3 (diff) | |
Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtl
Diffstat (limited to 'test/passes/split-exp/split-and.fir')
| -rw-r--r-- | test/passes/split-exp/split-and.fir | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/test/passes/split-exp/split-and.fir b/test/passes/split-exp/split-and.fir new file mode 100644 index 00000000..8eb4bdab --- /dev/null +++ b/test/passes/split-exp/split-and.fir @@ -0,0 +1,8 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s + +; CHECK: Done! +circuit Top : + module Top : + input a : SInt<2> + output c : UInt<2> + c <= and(a,asSInt(UInt(2))) |