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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/split-exp/print-args.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/split-exp/print-args.fir')
-rw-r--r--test/passes/split-exp/print-args.fir14
1 files changed, 0 insertions, 14 deletions
diff --git a/test/passes/split-exp/print-args.fir b/test/passes/split-exp/print-args.fir
deleted file mode 100644
index df21949d..00000000
--- a/test/passes/split-exp/print-args.fir
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-; CHECK: Split Expressions
-; CHECK: node GEN_0 = and(a, b)
-; CHECK: printf(clk, UInt<1>("h1"), "%d\n", GEN_0)
-
-circuit Bug :
- module Bug :
- input clk : Clock
- input a : UInt<1>
- input b : UInt<1>
-
- printf(clk, UInt<1>(1), "%d\n", and(a, b))
-