diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/split-exp/primop.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/split-exp/primop.fir')
| -rw-r--r-- | test/passes/split-exp/primop.fir | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir index b2f0af82..caccf57b 100644 --- a/test/passes/split-exp/primop.fir +++ b/test/passes/split-exp/primop.fir @@ -6,15 +6,15 @@ circuit Top : output out : UInt<1> wire m : UInt<1>[3] - m[0] := UInt(0) - m[1] := UInt(0) - m[2] := UInt(0) + m[0] <= UInt(0) + m[1] <= UInt(0) + m[2] <= UInt(0) wire x : UInt<1> - x := not(UInt(1)) + x <= not(UInt(1)) infer accessor a = m[x] - out := a + out <= a |