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| author | azidar | 2015-08-25 15:37:53 -0700 |
|---|---|---|
| committer | azidar | 2015-08-25 15:37:53 -0700 |
| commit | 40bf74bfdf4d07f0d7171b77ae34004eb9c1fa11 (patch) | |
| tree | bc64373fa3c59972731fa9167d8f65b47ccae9d5 /test/passes/split-exp/primop.fir | |
| parent | 9fd6d47c5ee82e4dac924e15b60f2a519d566b14 (diff) | |
Fixed bug in split expression that leaked connect statements out of a conditional assignment
Diffstat (limited to 'test/passes/split-exp/primop.fir')
| -rw-r--r-- | test/passes/split-exp/primop.fir | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/test/passes/split-exp/primop.fir b/test/passes/split-exp/primop.fir index 3b120217..b2f0af82 100644 --- a/test/passes/split-exp/primop.fir +++ b/test/passes/split-exp/primop.fir @@ -4,7 +4,6 @@ circuit Top : module Top : output out : UInt<1> - output out2 : UInt<1> wire m : UInt<1>[3] m[0] := UInt(0) |