diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/resolve-kinds | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/resolve-kinds')
| -rw-r--r-- | test/passes/resolve-kinds/gcd.fir | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 3583c81a..bb978972 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -16,14 +16,12 @@ circuit top : input e : UInt<1> output z : UInt<16> output v : UInt<1> - reg x : UInt,clk,reset - reg y : UInt,clk,reset - onreset x <= UInt(0) - onreset y <= UInt(42) + reg x : UInt,clk,reset,UInt(0) + reg y : UInt,clk,reset,UInt(42) when gt(x, y) : inst s of subtracter s.x <= x - ;CHECK: s@<k:inst>.x <= x@<k:reg> + ;CHECK: s@<k:inst>.x@<k:inst> <= x@<k:reg> s.y <= y x <= s.z else : @@ -43,14 +41,13 @@ circuit top : input reset : UInt<1> output z : UInt inst i of gcd - ;CHECK: inst i of gcd@<k:module> i.a <= a i.b <= b i.clk <= clk i.reset <= reset i.e <= UInt(1) z <= i.z - ;CHECK: z@<k:port> <= i@<k:inst>.z + ;CHECK: z@<k:port> <= i@<k:inst>.z@<k:inst> ; CHECK: Finished Resolve Kinds |