diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/resolve-genders/subbundle.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/resolve-genders/subbundle.fir')
| -rw-r--r-- | test/passes/resolve-genders/subbundle.fir | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir deleted file mode 100644 index e91fa52e..00000000 --- a/test/passes/resolve-genders/subbundle.fir +++ /dev/null @@ -1,14 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cT 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Lower Types -circuit top : - module top : - input clk : Clock - input reset : UInt<1> - wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>},clk with : - reset => (reset,w) - w <= r ; CHECK r_x := w_x - w.x <= r.x ; CHECK w_x := r_x -; CHECK: Finished Lower Types - |