diff options
| author | azidar | 2015-07-13 16:22:43 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | 271e1bf5ed56847c1ce7d50bdb7f1db9ccc5ea55 (patch) | |
| tree | 8b1cdfcfc97a9710bd1bc5be973578f712cfa253 /test/passes/resolve-genders/subbundle.fir | |
| parent | 0bfb3618b654a4082cc2780887b3ca32e374f455 (diff) | |
Added tests for clocks. Added remove scope and special chars passes. Added tests. Made more tests pass
Diffstat (limited to 'test/passes/resolve-genders/subbundle.fir')
| -rw-r--r-- | test/passes/resolve-genders/subbundle.fir | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 383c2a31..354545fb 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -3,8 +3,10 @@ ;CHECK: Lower To Ground circuit top : module top : + input clk : Clock + input reset : UInt<1> wire w : { flip x : UInt<10>} - reg r : { flip x : UInt<10>} + reg r : { flip x : UInt<10>},clk,reset w := r ; CHECK r$x := w$x w.x := r.x ; CHECK w$x := r$x ; CHECK: Finished Lower To Ground |