Updated all tests to pass

7 files changed, 64 insertions, 48 deletions

diff --git a/test/passes/remove-accesses/bundle-vecs.fir b/test/passes/remove-accesses/bundle-vecs.fir
index e916bfa8..e618892e 100644
--- a/test/passes/remove-accesses/bundle-vecs.fir
+++ b/test/passes/remove-accesses/bundle-vecs.fir
@@ -31,11 +31,11 @@ circuit top :
 ; CHECK: wire b : { x : UInt<32>, flip y : UInt<32>}
 ; CHECK: wire GEN_0 : UInt<32>
 ; CHECK: GEN_0 <= a[0].x
-; CHECK: when eqv(UInt("h1"), i) : GEN_0 <= a[1].x
+; CHECK: when eq(UInt("h1"), i) : GEN_0 <= a[1].x
 ; CHECK: b.x <= GEN_0
 ; CHECK: wire GEN_1 : UInt<32>
-; CHECK: when eqv(UInt("h0"), i) : a[0].y <= GEN_1
-; CHECK: when eqv(UInt("h1"), i) : a[1].y <= GEN_1
+; CHECK: when eq(UInt("h0"), i) : a[0].y <= GEN_1
+; CHECK: when eq(UInt("h1"), i) : a[1].y <= GEN_1
 ; CHECK: GEN_1 <= b.y
 ; CHECK: j <= b.x
 ; CHECK: b.y <= UInt("h1")   
diff --git a/test/passes/remove-accesses/simple11.fir b/test/passes/remove-accesses/simple11.fir
index e35bfb3c..b27f1a46 100644
--- a/test/passes/remove-accesses/simple11.fir
+++ b/test/passes/remove-accesses/simple11.fir
@@ -11,10 +11,14 @@ circuit DecoupledAdderTests :
     io.out.bits.c <= UInt<1>("h00")
     io.out.valid <= UInt<1>("h00")
     io.in.ready <= UInt<1>("h00")
-    reg ready : UInt<1>, clock, reset, ready
-    reg busy : UInt<1>, clock, reset, busy
-    reg a_reg : UInt<16>, clock, reset, a_reg
-    reg b_reg : UInt<16>, clock, reset, b_reg
+    reg ready : UInt<1>, clock with :
+       reset => ( reset, ready)
+    reg busy : UInt<1>, clock with :
+       reset => ( reset, busy)
+    reg a_reg : UInt<16>, clock with :
+       reset => ( reset, a_reg)
+    reg b_reg : UInt<16>, clock with :
+       reset => ( reset, b_reg)
     io.in.ready <= ready
     when io.in.valid :
       a_reg <= io.in.bits.a
@@ -25,7 +29,7 @@ circuit DecoupledAdderTests :
       skip
     node T_45 = and(busy, io.out.ready)
     when T_45 :
-      node T_46 = addw(a_reg, b_reg)
+      node T_46 = tail(add(a_reg, b_reg),1)
       io.out.bits.c <= T_46
       io.out.valid <= UInt<1>("h01")
       io.in.ready <= UInt<1>("h01")
@@ -44,8 +48,9 @@ circuit DecoupledAdderTests :
     device_under_test.io.in.valid <= UInt<1>("h00")
     device_under_test.clock <= clock
     device_under_test.reset <= reset
-    reg T_10 : UInt<33>, clock, reset, UInt<33>("h00")
-    node T_12 = addw(T_10, UInt<1>("h01"))
+    reg T_10 : UInt<33>, clock with :
+       reset => ( reset, UInt<33>("h00"))
+    node T_12 = tail(add(T_10, UInt<1>("h01")),1)
     T_10 <= T_12
     node T_14 = eq(reset, UInt<1>("h00"))
     when T_14 :
@@ -66,8 +71,10 @@ circuit DecoupledAdderTests :
     when T_22 :
       printf(clock,UInt(1), "device in ready %d, valid %d", device_under_test.io.in.ready, device_under_test.io.in.valid)
       skip
-    reg T_24 : UInt<1>, clock, reset, UInt<1>("h00")
-    reg T_26 : UInt<1>, clock, reset, UInt<1>("h00")
+    reg T_24 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
+    reg T_26 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
     node T_27 = and(T_24, T_26)
     when T_27 :
       node T_29 = eq(reset, UInt<1>("h00"))
@@ -75,8 +82,10 @@ circuit DecoupledAdderTests :
         stop(clock,UInt(1), 0)
         skip
       skip
-    reg T_31 : UInt<1>, clock, reset, UInt<1>("h00")
-    reg T_33 : UInt<1>, clock, reset, UInt<1>("h00")
+    reg T_31 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
+    reg T_33 : UInt<1>, clock with :
+       reset => ( reset, UInt<1>("h00"))
     wire T_43 : {flip ready : UInt<1>, valid : UInt<1>, bits : {a : UInt<16>, b : UInt<16>}}[1]
     T_43[0].bits.b <= UInt(0)
     T_43[0].bits.a <= UInt(1)
@@ -108,14 +117,14 @@ circuit DecoupledAdderTests :
     node T_113 = and(T_103, T_43[T_31].ready)
     when T_113 :
       T_43[T_31].valid <= UInt<1>("h01")
-      node T_125 = addw(T_31, UInt<1>("h01"))
+      node T_125 = tail(add(T_31, UInt<1>("h01")),1)
       T_31 <= T_125
       node T_127 = geq(T_31, UInt<1>("h00"))
       T_24 <= T_127
       skip
     node T_129 = eq(T_26, UInt<1>("h00"))
     when T_129 :
-      node T_131 = addw(T_33, UInt<1>("h01"))
+      node T_131 = tail(add(T_33, UInt<1>("h01")),1)
       T_33 <= T_131
       node T_133 = geq(T_33, UInt<1>("h00"))
       T_26 <= T_133
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir
index b19c4130..6305e0c9 100644
--- a/test/passes/remove-accesses/simple3.fir
+++ b/test/passes/remove-accesses/simple3.fir
@@ -13,8 +13,8 @@ circuit top :
       a <= in
 
 ;CHECK: wire GEN_0 : UInt<32>
-;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0
-;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0
+;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0
+;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0
 ;CHECK: GEN_0 <= a
 
 ;CHECK: Finished Remove Accesses
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
index 06ff7481..4766214c 100644
--- a/test/passes/remove-accesses/simple4.fir
+++ b/test/passes/remove-accesses/simple4.fir
@@ -12,8 +12,8 @@ circuit top :
       m[1].y <= UInt("h1")
       m[i].x <= in.x
 
-;CHECK: when eqv(UInt("h0"), i) : m[0].x <= GEN_0
-;CHECK: when eqv(UInt("h1"), i) : m[1].x <= GEN_0
+;CHECK: when eq(UInt("h0"), i) : m[0].x <= GEN_0
+;CHECK: when eq(UInt("h1"), i) : m[1].x <= GEN_0
 ;CHECK: GEN_0 <= in
 ;CHECK: Finished Remove Accesses
 ;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir
index 0a1baed6..d2e31537 100644
--- a/test/passes/remove-accesses/simple5.fir
+++ b/test/passes/remove-accesses/simple5.fir
@@ -15,7 +15,7 @@ circuit top :
 
 ;CHECK: when i :
 ;CHECK: GEN_0 <= m[0]
-;CHECK: when eqv(UInt("h1"), i) : GEN_0 <= m[1]
+;CHECK: when eq(UInt("h1"), i) : GEN_0 <= m[1]
 ;CHECK: o <= GEN_0
 ;CHECK: Finished Remove Accesses
 ;CHECK: Done!
diff --git a/test/passes/remove-accesses/simple8.fir b/test/passes/remove-accesses/simple8.fir
index 6b084ed3..1d275618 100644
--- a/test/passes/remove-accesses/simple8.fir
+++ b/test/passes/remove-accesses/simple8.fir
@@ -21,25 +21,26 @@ circuit top :
     wire T_75 : UInt<128>[2]
     T_75[0] <= UInt<1>("h00")
     T_75[1] <= UInt<1>("h00")
-    reg T_81 : UInt<12>, clock, reset, T_81
+    reg T_81 : UInt<12>, clock with :
+       reset => ( reset, T_81)
     when read.valid :
       T_81 <= read.bits.addr
       skip
     cmem T_84 : UInt<128>[256]
     node T_86 = neq(T_65, UInt<1>("h00"))
     node T_87 = and(T_86, write.valid)
-    node T_88 = bit(write.bits.wmask, 0)
+    node T_88 = bits(write.bits.wmask, 0, 0)
     node T_89 = and(T_87, T_88)
     when T_89 :
       node T_90 = bits(write.bits.data, 63, 0)
       node T_91 = cat(T_90, T_90)
-      node T_92 = bit(T_65, 0)
-      node T_93 = bit(T_65, 1)
+      node T_92 = bits(T_65, 0, 0)
+      node T_93 = bits(T_65, 1, 1)
       wire T_95 : UInt<1>[2]
       T_95[0] <= T_92
       T_95[1] <= T_93
-      node T_100 = subw(UInt<64>("h00"), T_95[0])
-      node T_102 = subw(UInt<64>("h00"), T_95[1])
+      node T_100 = tail(sub(UInt<64>("h00"), T_95[0]),1)
+      node T_102 = tail(sub(UInt<64>("h00"), T_95[1]),1)
       wire T_104 : UInt<64>[2]
       T_104[0] <= T_100
       T_104[1] <= T_102
@@ -57,7 +58,8 @@ circuit top :
       skip
     node T_118 = neq(T_66, UInt<1>("h00"))
     node T_119 = and(T_118, read.valid)
-    reg T_120 : UInt<8>, clock, reset, T_120
+    reg T_120 : UInt<8>, clock with :
+       reset => ( reset, T_120)
     when T_119 :
       T_120 <= raddr
       skip
@@ -66,18 +68,18 @@ circuit top :
     cmem T_124 : UInt<128>[256]
     node T_126 = neq(T_65, UInt<1>("h00"))
     node T_127 = and(T_126, write.valid)
-    node T_128 = bit(write.bits.wmask, 1)
+    node T_128 = bits(write.bits.wmask, 1, 1)
     node T_129 = and(T_127, T_128)
     when T_129 :
       node T_130 = bits(write.bits.data, 127, 64)
       node T_131 = cat(T_130, T_130)
-      node T_132 = bit(T_65, 0)
-      node T_133 = bit(T_65, 1)
+      node T_132 = bits(T_65, 0, 0)
+      node T_133 = bits(T_65, 1, 1)
       wire T_135 : UInt<1>[2]
       T_135[0] <= T_132
       T_135[1] <= T_133
-      node T_140 = subw(UInt<64>("h00"), T_135[0])
-      node T_142 = subw(UInt<64>("h00"), T_135[1])
+      node T_140 = tail(sub(UInt<64>("h00"), T_135[0]),1)
+      node T_142 = tail(sub(UInt<64>("h00"), T_135[1]),1)
       wire T_144 : UInt<64>[2]
       T_144[0] <= T_140
       T_144[1] <= T_142
@@ -95,7 +97,8 @@ circuit top :
       skip
     node T_158 = neq(T_66, UInt<1>("h00"))
     node T_159 = and(T_158, read.valid)
-    reg T_160 : UInt<8>, clock, reset, T_160
+    reg T_160 : UInt<8>, clock with :
+       reset => ( reset, T_160)
     when T_159 :
       T_160 <= raddr
       skip
@@ -128,25 +131,26 @@ circuit top :
     wire T_202 : UInt<128>[2]
     T_202[0] <= UInt<1>("h00")
     T_202[1] <= UInt<1>("h00")
-    reg T_208 : UInt<12>, clock, reset, T_208
+    reg T_208 : UInt<12>, clock with :
+       reset => ( reset, T_208)
     when read.valid :
       T_208 <= read.bits.addr
       skip
     cmem T_211 : UInt<128>[256]
     node T_213 = neq(T_192, UInt<1>("h00"))
     node T_214 = and(T_213, write.valid)
-    node T_215 = bit(write.bits.wmask, 0)
+    node T_215 = bits(write.bits.wmask, 0, 0)
     node T_216 = and(T_214, T_215)
     when T_216 :
       node T_217 = bits(write.bits.data, 63, 0)
       node T_218 = cat(T_217, T_217)
-      node T_219 = bit(T_192, 0)
-      node T_220 = bit(T_192, 1)
+      node T_219 = bits(T_192, 0, 0)
+      node T_220 = bits(T_192, 1, 1)
       wire T_222 : UInt<1>[2]
       T_222[0] <= T_219
       T_222[1] <= T_220
-      node T_227 = subw(UInt<64>("h00"), T_222[0])
-      node T_229 = subw(UInt<64>("h00"), T_222[1])
+      node T_227 = tail(sub(UInt<64>("h00"), T_222[0]),1)
+      node T_229 = tail(sub(UInt<64>("h00"), T_222[1]),1)
       wire T_231 : UInt<64>[2]
       T_231[0] <= T_227
       T_231[1] <= T_229
@@ -164,7 +168,8 @@ circuit top :
       skip
     node T_245 = neq(T_193, UInt<1>("h00"))
     node T_246 = and(T_245, read.valid)
-    reg T_247 : UInt<8>, clock, reset, T_247
+    reg T_247 : UInt<8>, clock with :
+       reset => ( reset, T_247)
     when T_246 :
       T_247 <= raddr
       skip
@@ -173,18 +178,18 @@ circuit top :
     cmem T_251 : UInt<128>[256]
     node T_253 = neq(T_192, UInt<1>("h00"))
     node T_254 = and(T_253, write.valid)
-    node T_255 = bit(write.bits.wmask, 1)
+    node T_255 = bits(write.bits.wmask, 1, 1)
     node T_256 = and(T_254, T_255)
     when T_256 :
       node T_257 = bits(write.bits.data, 127, 64)
       node T_258 = cat(T_257, T_257)
-      node T_259 = bit(T_192, 0)
-      node T_260 = bit(T_192, 1)
+      node T_259 = bits(T_192, 0, 0)
+      node T_260 = bits(T_192, 1, 1)
       wire T_262 : UInt<1>[2]
       T_262[0] <= T_259
       T_262[1] <= T_260
-      node T_267 = subw(UInt<64>("h00"), T_262[0])
-      node T_269 = subw(UInt<64>("h00"), T_262[1])
+      node T_267 = tail(sub(UInt<64>("h00"), T_262[0]),1)
+      node T_269 = tail(sub(UInt<64>("h00"), T_262[1]),1)
       wire T_271 : UInt<64>[2]
       T_271[0] <= T_267
       T_271[1] <= T_269
@@ -202,7 +207,8 @@ circuit top :
       skip
     node T_285 = neq(T_193, UInt<1>("h00"))
     node T_286 = and(T_285, read.valid)
-    reg T_287 : UInt<8>, clock, reset, T_287
+    reg T_287 : UInt<8>, clock with :
+       reset => ( reset, T_287)
     when T_286 :
       T_287 <= raddr
       skip
diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir
index 5405c42a..d1aec9f1 100644
--- a/test/passes/remove-accesses/simple9.fir
+++ b/test/passes/remove-accesses/simple9.fir
@@ -7,7 +7,8 @@ circuit top :
     input reset : UInt<1>
     input clock : Clock
     output out : UInt<1>
-    reg T_4590 : UInt<1>[2], clock, reset, T_4590
+    reg T_4590 : UInt<1>[2], clock with :
+       reset => ( reset, T_4590)
     T_4590[0] <= UInt(0)
     T_4590[1] <= UInt(0)
     out <= UInt(0)