diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/remove-accesses/simple9.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/remove-accesses/simple9.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple9.fir | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/passes/remove-accesses/simple9.fir b/test/passes/remove-accesses/simple9.fir index 5405c42a..d1aec9f1 100644 --- a/test/passes/remove-accesses/simple9.fir +++ b/test/passes/remove-accesses/simple9.fir @@ -7,7 +7,8 @@ circuit top : input reset : UInt<1> input clock : Clock output out : UInt<1> - reg T_4590 : UInt<1>[2], clock, reset, T_4590 + reg T_4590 : UInt<1>[2], clock with : + reset => ( reset, T_4590) T_4590[0] <= UInt(0) T_4590[1] <= UInt(0) out <= UInt(0) |