diff options
| author | azidar | 2016-01-16 15:49:30 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 15:49:30 -0800 |
| commit | 81e47120c8586871fd96e22e0626591d3b5a7cc5 (patch) | |
| tree | 46bab805ee6e0a49b69f3e7870f5a8c7013957f3 /test/passes/remove-accesses/simple7.fir | |
| parent | df1bb3aced1e560dd919460a846c28ad2deacbd3 (diff) | |
Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore
Diffstat (limited to 'test/passes/remove-accesses/simple7.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple7.fir | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/test/passes/remove-accesses/simple7.fir b/test/passes/remove-accesses/simple7.fir new file mode 100644 index 00000000..5dfd5ce3 --- /dev/null +++ b/test/passes/remove-accesses/simple7.fir @@ -0,0 +1,11 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +circuit top : + module top : + output out : UInt<64> + input index : UInt<1> + wire T_292 : UInt<64>[2] + T_292[0] <= UInt(1) + T_292[1] <= UInt(1) + out <= T_292[index] +;CHECK: Done! |