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| author | azidar | 2016-01-16 15:49:51 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 15:49:51 -0800 |
| commit | ea9cb9c8b34b78e3bc4d0bd474521b60acfbbc26 (patch) | |
| tree | d3e8cce922d4fc1b40e9d41e1c05b3d843107387 /test/passes/remove-accesses/simple5.fir | |
| parent | 9dcb5684957e684174d97a45f80d1cfad887a741 (diff) | |
| parent | 81e47120c8586871fd96e22e0626591d3b5a7cc5 (diff) | |
Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem
Diffstat (limited to 'test/passes/remove-accesses/simple5.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple5.fir | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/test/passes/remove-accesses/simple5.fir b/test/passes/remove-accesses/simple5.fir new file mode 100644 index 00000000..099f020c --- /dev/null +++ b/test/passes/remove-accesses/simple5.fir @@ -0,0 +1,21 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s + +;CHECK: Remove Accesses +circuit top : + module top : + output o : UInt + o <= UInt(1) + wire m : UInt<32>[2] + wire i : UInt + m[0] <= UInt("h1") + m[1] <= UInt("h1") + i <= UInt("h1") + when i : + o <= m[i] + +;CHECK: when i : +;CHECK: GEN <= m[0] +;CHECK: when eqv(UInt("h1"), i) : GEN <= m[1] +;CHECK: o <= GEN +;CHECK: Finished Remove Accesses +;CHECK: Done! |