aboutsummaryrefslogtreecommitdiff
path: root/test/passes/remove-accesses/simple4.fir
diff options
context:
space:
mode:
authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/remove-accesses/simple4.fir
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/remove-accesses/simple4.fir')
-rw-r--r--test/passes/remove-accesses/simple4.fir22
1 files changed, 0 insertions, 22 deletions
diff --git a/test/passes/remove-accesses/simple4.fir b/test/passes/remove-accesses/simple4.fir
deleted file mode 100644
index f4f3a6a5..00000000
--- a/test/passes/remove-accesses/simple4.fir
+++ /dev/null
@@ -1,22 +0,0 @@
-; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-
-;CHECK: Remove Accesses
-circuit top :
- module top :
- input in : {x : UInt<32>, y : UInt<32>}
- input i : UInt<1>
- wire m : {x : UInt<32>, y : UInt<32>}[2]
- m[0].x <= UInt("h1")
- m[0].y <= UInt("h1")
- m[1].x <= UInt("h1")
- m[1].y <= UInt("h1")
- m[i].x <= in.x
-
-;CHECK: when eq(UInt<1>("h0"), i) : m[0].x <= GEN_0
-;CHECK: when eq(UInt<1>("h1"), i) : m[1].x <= GEN_0
-;CHECK: GEN_0 <= in
-;CHECK: Finished Remove Accesses
-;CHECK: Done!
-
-
-