diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/remove-accesses/simple3.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/remove-accesses/simple3.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple3.fir | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/remove-accesses/simple3.fir b/test/passes/remove-accesses/simple3.fir index b19c4130..6305e0c9 100644 --- a/test/passes/remove-accesses/simple3.fir +++ b/test/passes/remove-accesses/simple3.fir @@ -13,8 +13,8 @@ circuit top : a <= in ;CHECK: wire GEN_0 : UInt<32> -;CHECK: when eqv(UInt("h0"), i) : m[0] <= GEN_0 -;CHECK: when eqv(UInt("h1"), i) : m[1] <= GEN_0 +;CHECK: when eq(UInt("h0"), i) : m[0] <= GEN_0 +;CHECK: when eq(UInt("h1"), i) : m[1] <= GEN_0 ;CHECK: GEN_0 <= a ;CHECK: Finished Remove Accesses |