Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignore

1 files changed, 16 insertions, 0 deletions

diff --git a/test/passes/remove-accesses/simple2.fir b/test/passes/remove-accesses/simple2.fir
new file mode 100644
index 00000000..ee6b5923
--- /dev/null
+++ b/test/passes/remove-accesses/simple2.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+   module top :
+      output o1 : UInt
+      output o2 : UInt
+      wire m : UInt<32>[2]
+      wire i : UInt
+      m[0] <= UInt("h1")
+      m[1] <= UInt("h1")
+      i <= UInt("h1")
+      node a = m[i] 
+      o1 <= a
+      o2 <= a
+
+;CHECK: Done!