diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/remove-accesses/simple10.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/remove-accesses/simple10.fir')
| -rw-r--r-- | test/passes/remove-accesses/simple10.fir | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/test/passes/remove-accesses/simple10.fir b/test/passes/remove-accesses/simple10.fir deleted file mode 100644 index b213f372..00000000 --- a/test/passes/remove-accesses/simple10.fir +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p cg 2>&1 | tee %s.out | FileCheck %s - -;CHECK: Done! - -circuit DecoupledAdderTests : - module DecoupledAdderTests : - input clock : Clock - input reset : UInt<1> - input T_31 : UInt<1> - input T_68 : UInt<1> - output out : UInt - output io : {} - wire T_43 : {flip ready : UInt<1>}[1] - T_43[0].ready <= UInt(0) - node T_78 = and(T_68, T_43[T_31].ready) - out <= T_78 |