diff options
| author | Adam Izraelevitz | 2016-08-15 10:32:41 -0700 |
|---|---|---|
| committer | GitHub | 2016-08-15 10:32:41 -0700 |
| commit | bebd04c4c68c320b2b72325e348c726dc33beae6 (patch) | |
| tree | 69f6d4da577977cc7ff428b0545bb4735507aad0 /test/passes/remove-accesses/init-vecs.fir | |
| parent | cca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff) | |
Remove stanza (#231)
* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
Diffstat (limited to 'test/passes/remove-accesses/init-vecs.fir')
| -rw-r--r-- | test/passes/remove-accesses/init-vecs.fir | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/test/passes/remove-accesses/init-vecs.fir b/test/passes/remove-accesses/init-vecs.fir deleted file mode 100644 index d8eeec88..00000000 --- a/test/passes/remove-accesses/init-vecs.fir +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s - -circuit top : - module top : - wire outs : UInt<32>[2][1] - outs[0][0] <= UInt(1) - outs[0][1] <= UInt(1) - - wire out : UInt<32>[2] - out <= outs[UInt(0)] - out[0] <= UInt(1) - -; CHECK: Done! - - |