Merge branch 'new-mem' of github.com:ucb-bar/firrtl into scala-new-mem

1 files changed, 15 insertions, 0 deletions

diff --git a/test/passes/remove-accesses/init-vecs.fir b/test/passes/remove-accesses/init-vecs.fir
new file mode 100644
index 00000000..d8eeec88
--- /dev/null
+++ b/test/passes/remove-accesses/init-vecs.fir
@@ -0,0 +1,15 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+
+circuit top :
+   module top :
+      wire outs : UInt<32>[2][1]
+      outs[0][0] <= UInt(1)
+      outs[0][1] <= UInt(1)
+
+      wire out : UInt<32>[2]
+      out <= outs[UInt(0)]
+      out[0] <= UInt(1)
+
+; CHECK: Done!
+
+