diff options
| author | azidar | 2016-01-07 17:15:31 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:18 -0800 |
| commit | 4569194392122ae4715549b2f0b9fffff051b278 (patch) | |
| tree | ecd079cefa6fb69d1f8c75bc0e75e38599bc0da4 /test/passes/lower-to-ground | |
| parent | 2d583abda146dad8e0260928dcb19ad7136216b6 (diff) | |
Fixed a bunch of tests, and minor bugs
Diffstat (limited to 'test/passes/lower-to-ground')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 24 | ||||
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 2 |
2 files changed, 13 insertions, 13 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 719033cb..9821f69b 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -25,20 +25,20 @@ circuit top : ;CHECK: wire GEN_3 : UInt<32> ;CHECK: j_x <= GEN ;CHECK: j_y <= GEN_3 -;CHECK: node a_0_x = eqv(UInt("h0"), i) -;CHECK: a_0_x <= mux(a_0_x, GEN_2, UInt("h0")) -;CHECK: node a_0_y = eqv(UInt("h0"), i) -;CHECK: a_0_y <= mux(a_0_y, GEN_1, UInt("h0")) -;CHECK: node a_1_x = eqv(UInt("h1"), i) -;CHECK: a_1_x <= mux(a_1_x, GEN_2, UInt("h0")) -;CHECK: node a_1_y = eqv(UInt("h1"), i) -;CHECK: a_1_y <= mux(a_1_y, GEN_1, UInt("h0")) -;CHECK: node GEN_4 = eqv(UInt("h1"), i) -;CHECK: GEN <= mux(GEN_4, a_1_x, a_0_x) +;CHECK: node GEN_4 = eqv(UInt("h0"), i) +;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) +;CHECK: node GEN_5 = eqv(UInt("h0"), i) +;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0")) +;CHECK: node GEN_6 = eqv(UInt("h1"), i) +;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0")) +;CHECK: node GEN_7 = eqv(UInt("h1"), i) +;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) +;CHECK: node GEN_8 = eqv(UInt("h1"), i) +;CHECK: GEN <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x -;CHECK: node GEN_5 = eqv(UInt("h1"), i) -;CHECK: GEN_3 <= mux(GEN_5, a_1_y, a_0_y) +;CHECK: node GEN_9 = eqv(UInt("h1"), i) +;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y) ; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index b2ea2d63..a8f8ad78 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -4,7 +4,7 @@ circuit top : module m : input a : { x : UInt<5>, flip y: SInt<5>} output b : { x : UInt<5>, flip y: SInt<5>} - a.y <= UInt(0) + a.y <= SInt(0) b.x <= UInt(0) module top : input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } |