diff options
| author | azidar | 2016-01-25 11:29:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-25 11:29:45 -0800 |
| commit | f6ea3dc1bb5efb4455fd3b995ced36add85a44c0 (patch) | |
| tree | dbc0135e3a4ef0ac387fa9fe02b6f7bba2d4dbe5 /test/passes/lower-to-ground | |
| parent | a637f4f0cedadf5e81fc9d9d3b1392daf99db603 (diff) | |
Changed tests to pass with change to postfix of generated name
Diffstat (limited to 'test/passes/lower-to-ground')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 9821f69b..64a4a4b6 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -19,11 +19,11 @@ circuit top : j <= a[i] a[i] <= j -;CHECK: wire GEN : UInt<32> +;CHECK: wire GEN_0 : UInt<32> ;CHECK: wire GEN_1 : UInt<32> ;CHECK: wire GEN_2 : UInt<32> ;CHECK: wire GEN_3 : UInt<32> -;CHECK: j_x <= GEN +;CHECK: j_x <= GEN_0 ;CHECK: j_y <= GEN_3 ;CHECK: node GEN_4 = eqv(UInt("h0"), i) ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) @@ -34,7 +34,7 @@ circuit top : ;CHECK: node GEN_7 = eqv(UInt("h1"), i) ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) ;CHECK: node GEN_8 = eqv(UInt("h1"), i) -;CHECK: GEN <= mux(GEN_8, a_1_x, a_0_x) +;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x ;CHECK: node GEN_9 = eqv(UInt("h1"), i) |