diff options
| author | azidar | 2016-01-31 12:59:31 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:57:06 -0800 |
| commit | e985d47312458459e9ebe42fe99b5a063c08e637 (patch) | |
| tree | d726c711e86d6e948a220a568dcae0a997629d18 /test/passes/lower-to-ground | |
| parent | 2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff) | |
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/lower-to-ground')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 12 | ||||
| -rw-r--r-- | test/passes/lower-to-ground/nested-vec.fir | 8 |
2 files changed, 10 insertions, 10 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index cf581ab7..d6af7a82 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -25,14 +25,14 @@ circuit top : ; CHECK: wire GEN_3 : UInt<32> ; CHECK: j_x <= GEN_0 ; CHECK: j_y <= GEN_3 -; CHECK: a_0_x <= mux(eq(UInt("h0"), i), GEN_2, UInt("h0")) -; CHECK: a_0_y <= mux(eq(UInt("h0"), i), GEN_1, UInt("h0")) -; CHECK: a_1_x <= mux(eq(UInt("h1"), i), GEN_2, UInt("h0")) -; CHECK: a_1_y <= mux(eq(UInt("h1"), i), GEN_1, UInt("h0")) -; CHECK: GEN_0 <= mux(eq(UInt("h1"), i), a_1_x, a_0_x) +; CHECK: a_0_x <= mux(eq(UInt<1>("h0"), i), GEN_2, UInt<1>("h0")) +; CHECK: a_0_y <= mux(eq(UInt<1>("h0"), i), GEN_1, UInt<1>("h0")) +; CHECK: a_1_x <= mux(eq(UInt<1>("h1"), i), GEN_2, UInt<1>("h0")) +; CHECK: a_1_y <= mux(eq(UInt<1>("h1"), i), GEN_1, UInt<1>("h0")) +; CHECK: GEN_0 <= mux(eq(UInt<1>("h1"), i), a_1_x, a_0_x) ; CHECK: GEN_1 <= j_y ; CHECK: GEN_2 <= j_x -; CHECK: GEN_3 <= mux(eq(UInt("h1"), i), a_1_y, a_0_y) +; CHECK: GEN_3 <= mux(eq(UInt<1>("h1"), i), a_1_y, a_0_y) ; CHECK: Finished Lower Types diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index fcdee5bc..7f9306ce 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -54,12 +54,12 @@ circuit top : ;CHECK: writer => c ;CHECK: m_x.c.data <= k_x ;CHECK: m_y.c.data <= k_y -;CHECK: m_x.c.mask <= UInt("h1") -;CHECK: m_y.c.mask <= UInt("h1") +;CHECK: m_x.c.mask <= UInt<1>("h1") +;CHECK: m_y.c.mask <= UInt<1>("h1") ;CHECK: m_x.c.addr <= i ;CHECK: m_y.c.addr <= i -;CHECK: m_x.c.en <= UInt("h1") -;CHECK: m_y.c.en <= UInt("h1") +;CHECK: m_x.c.en <= UInt<1>("h1") +;CHECK: m_y.c.en <= UInt<1>("h1") ;CHECK: m_x.c.clk <= clk ;CHECK: m_y.c.clk <= clk |