Finished expand accessors and lower to ground

4 files changed, 151 insertions, 0 deletions

diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
new file mode 100644
index 00000000..56171246
--- /dev/null
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -0,0 +1,33 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module m :
+      wire i : UInt
+      wire j : UInt
+
+      wire a : UInt(32)[4]
+      ; CHECK: wire a#0 : UInt(32)
+      ; CHECK: wire a#1 : UInt(32)
+      ; CHECK: wire a#2 : UInt(32)
+      ; CHECK: wire a#3 : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b : UInt(32)
+      ; CHECK: b := (a#0 a#1 a#2 a#3)[i]
+      j := b
+
+      accessor c = a[i]
+      ; CHECK: wire c : UInt(32)
+      ; CHECK: (a#0 a#1 a#2 a#3)[i] := c
+      c := j
+      
+      mem p : UInt(32)[10]
+      accessor t = p[i]
+      ; CHECK: accessor t = p[i]
+      j := t
+      accessor r = p[i]
+      ; CHECK: accessor r = p[i]
+      r := j
+
+; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
new file mode 100644
index 00000000..a4ead6ed
--- /dev/null
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module q :
+      wire i : UInt
+      wire j : UInt
+
+      wire a : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: wire a#0#x : UInt(32)
+      ; CHECK: wire a#0#y : UInt(32)
+      ; CHECK: wire a#1#x : UInt(32)
+      ; CHECK: wire a#1#y : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b#x : UInt(32)
+      ; CHECK: wire b#y : UInt(32)
+      ; CHECK: b#x := (a#0#x a#1#x)[i]
+      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      j := b
+      
+      accessor c = a[i]
+      ; CHECK: wire c#x : UInt(32)
+      ; CHECK: wire c#y : UInt(32)
+      ; CHECK: (a#0#x a#1#x)[i] := c#x
+      ; CHECK: c#y := (a#0#y a#1#y)[i]
+      c := j
+
+
+; CHECK: Finished Lower To Ground
+
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
new file mode 100644
index 00000000..990b6b7f
--- /dev/null
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -0,0 +1,53 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+circuit top :
+   module m :
+      input  a : { x : UInt, flip y: SInt}
+      output b : { x : UInt, flip y: SInt}
+   module subtracter :
+      input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } }
+      wire a : { x : UInt, flip y : SInt}
+      wire b : { x : UInt, flip y : SInt}
+      a := b
+      inst i of m
+      i.a := a
+      b := i.b
+      wire d : UInt[5]
+
+;CHECK: Lower To Ground
+;CHECK: circuit top :
+;CHECK:    module m :
+;CHECK:       input a#x : UInt
+;CHECK:       output a#y : SInt
+;CHECK:       output b#x : UInt
+;CHECK:       input b#y : SInt
+;CHECK:       input reset : UInt(1)
+;CHECK:    module subtracter :
+;CHECK:       input c#x#0 : UInt
+;CHECK:       input c#x#1 : UInt
+;CHECK:       input c#x#2 : UInt
+;CHECK:       input c#x#3 : UInt
+;CHECK:       input c#x#4 : UInt
+;CHECK:       output c#y#x#0 : UInt
+;CHECK:       output c#y#x#1 : UInt
+;CHECK:       output c#y#x#2 : UInt
+;CHECK:       input c#y#y : SInt
+;CHECK:       input reset : UInt(1)
+;CHECK:       wire a#x : UInt
+;CHECK:       wire a#y : SInt
+;CHECK:       wire b#x : UInt
+;CHECK:       wire b#y : SInt
+;CHECK:       a#x := b#x
+;CHECK:       b#y := a#y
+;CHECK:       inst i of m
+;CHECK:       i.reset := reset
+;CHECK:       i.a#x := a#x
+;CHECK:       a#y := i.a#y
+;CHECK:       b#x := i.b#x
+;CHECK:       i.b#y := b#y
+;CHECK:       wire d#0 : UInt
+;CHECK:       wire d#1 : UInt
+;CHECK:       wire d#2 : UInt
+;CHECK:       wire d#3 : UInt
+;CHECK:       wire d#4 : UInt
+;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
new file mode 100644
index 00000000..8eafb8e8
--- /dev/null
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -0,0 +1,34 @@
+; RUN: firrtl %s abcdefgh c | tee %s.out | FileCheck %s
+
+; CHECK: Lower To Ground
+circuit top :
+   module q :
+      wire i : UInt
+      wire j : { x : UInt(32), flip y : UInt(32) }
+
+      wire a : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: wire a#0#x : UInt(32)
+      ; CHECK: wire a#0#y : UInt(32)
+      ; CHECK: wire a#1#x : UInt(32)
+      ; CHECK: wire a#1#y : UInt(32)
+
+      accessor b = a[i]
+      ; CHECK: wire b#x : UInt(32)
+      ; CHECK: wire b#y : UInt(32)
+      ; CHECK: b#x := (a#0#x a#1#x)[i]
+      ; CHECK: (a#0#y a#1#y)[i] := b#y
+      j := b
+
+      mem m : { x : UInt(32), flip y : UInt(32) }[2]
+      ; CHECK: mem m#x : UInt(32)[2]
+      ; CHECK: mem m#y : UInt(32)[2]
+
+      accessor c = m[i] ; MALE
+      ; CHECK: accessor c#x = m#x[i]
+      ; CHECK: accessor c#y = m#y[i]
+      ; CHECK: c#x := j#x
+      ; CHECK: j#y := c#y
+      c := j
+
+; CHECK: Finished Lower To Ground
+