New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

7 files changed, 36 insertions, 36 deletions

diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 4d55d0f6..c712fdc2 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -15,18 +15,18 @@ circuit top :
 
       infer accessor b = a[i]
       ; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32>
-      j := b
+      j <= b
 
       infer accessor c = a[i]
       ; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32>
-      c := j
+      c <= j
       
       cmem p : UInt<32>[4],clk
       infer accessor t = p[i]
       ; CHECK: read accessor t = p[i]
-      j := t
+      j <= t
       infer accessor r = p[i]
       ; CHECK: write accessor r = p[i]
-      r := j
+      r <= j
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 7d37e65c..b0de26f4 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -15,12 +15,12 @@ circuit top :
       infer accessor b = a[i]
       ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32>
       ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32>
-      j := b
+      j <= b
       
       infer accessor c = a[i]
       ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32>
       ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32>
-      c := j
+      c <= j
 
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 06558e44..ccf942ee 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -8,10 +8,10 @@ circuit top :
       input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } }
       wire a : { x : UInt<5>, flip y : SInt<5>}
       wire b : { x : UInt<5>, flip y : SInt<5>}
-      a := b
+      a <= b
       inst i of m
-      i.a := a
-      b := i.b
+      i.a <= a
+      b <= i.b
       wire d : UInt<5>[5]
 
 ;CHECK: Lower To Ground
@@ -35,13 +35,13 @@ circuit top :
 ;CHECK:       wire a{{[_$]+}}y : SInt<5>
 ;CHECK:       wire b{{[_$]+}}x : UInt<5>
 ;CHECK:       wire b{{[_$]+}}y : SInt<5>
-;CHECK:       a{{[_$]+}}x := b{{[_$]+}}x
-;CHECK:       b{{[_$]+}}y := a{{[_$]+}}y
+;CHECK:       a{{[_$]+}}x <= b{{[_$]+}}x
+;CHECK:       b{{[_$]+}}y <= a{{[_$]+}}y
 ;CHECK:       inst i of m
-;CHECK:       i.a{{[_$]+}}x := a{{[_$]+}}x
-;CHECK:       a{{[_$]+}}y := i.a{{[_$]+}}y
-;CHECK:       b{{[_$]+}}x := i.b{{[_$]+}}x
-;CHECK:       i.b{{[_$]+}}y := b{{[_$]+}}y
+;CHECK:       i.a{{[_$]+}}x <= a{{[_$]+}}x
+;CHECK:       a{{[_$]+}}y <= i.a{{[_$]+}}y
+;CHECK:       b{{[_$]+}}x <= i.b{{[_$]+}}x
+;CHECK:       i.b{{[_$]+}}y <= b{{[_$]+}}y
 ;CHECK:       wire d{{[_$]+}}0 : UInt<5>
 ;CHECK:       wire d{{[_$]+}}1 : UInt<5>
 ;CHECK:       wire d{{[_$]+}}2 : UInt<5>
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 8d6beb93..ecc2d40b 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -4,7 +4,7 @@ circuit top :
    module source :
       output data : UInt<16>
       input ready : UInt<1>
-      data := UInt(16)
+      data <= UInt(16)
    module sink :
       input data : UInt<16>
       output ready : UInt<1>
@@ -13,23 +13,23 @@ circuit top :
       wire connect2 : { flip data : UInt<16>, ready: UInt<1> }
       inst src of source         
       inst snk of sink           
-      connect := src   
-      connect2 := snk
+      connect <= src   
+      connect2 <= snk
 
 
 ; CHECK: Resolve Genders
 
-; CHECK: connect@<g:f> := src@<g:m>
-; CHECK: connect2@<g:f> := snk@<g:m>
+; CHECK: connect@<g:f> <= src@<g:m>
+; CHECK: connect2@<g:f> <= snk@<g:m>
 
 ; CHECK: Finished Resolve Genders
 
 
 ; CHECK: Lower To Ground
 
-; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m>
-; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m>
+; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index aa208b01..0c58f267 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -17,7 +17,7 @@ circuit top :
       infer accessor b = a[i]
       ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32>
       ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32>
-      j := b
+      j <= b
 
       cmem m : { x : UInt<32>, y : UInt<32> }[2],clk
       ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2]
@@ -27,9 +27,9 @@ circuit top :
       ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i]
       ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i]
 
-      c := k
-      ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x
-      ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y
+      c <= k
+      ; CHECK: c{{[_$]+}}x <= k{{[_$]+}}x
+      ; CHECK: c{{[_$]+}}y <= k{{[_$]+}}y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 75b4fe88..99f63153 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,13 +11,13 @@
 
                reg r1 : { x : UInt, y : SInt },clk,reset
                wire q : { x : UInt, y : SInt }
-               onreset r1 := q    
+               onreset r1 <= q    
 
       ; CHECK: reg r1{{[_$]+}}x : UInt
       ; CHECK: reg r1{{[_$]+}}y : SInt
       ; CHECK: wire q{{[_$]+}}x : UInt
       ; CHECK: wire q{{[_$]+}}y : SInt
-      ; CHECK: onreset r1{{[_$]+}}x := q{{[_$]+}}x
-      ; CHECK: onreset r1{{[_$]+}}y := q{{[_$]+}}y
+      ; CHECK: onreset r1{{[_$]+}}x <= q{{[_$]+}}x
+      ; CHECK: onreset r1{{[_$]+}}y <= q{{[_$]+}}y
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir
index db78da84..4cf61462 100644
--- a/test/passes/lower-to-ground/test.fir
+++ b/test/passes/lower-to-ground/test.fir
@@ -4,13 +4,13 @@
 circuit Top :
   module Queue :
     output out : {valid : UInt<1>, flip ready : UInt<1>}
-    out.valid := UInt(1)
+    out.valid <= UInt(1)
   module Top :
     output this : {out : {valid : UInt<1>, flip ready : UInt<1>}}
     inst queue of Queue
-    this.out := queue.out
+    this.out <= queue.out
     wire w : { x : UInt<5>, flip y : UInt<5>}
-    w.x := UInt(1)
+    w.x <= UInt(1)
     wire a : UInt<5>
-    a := UInt(1)
-    w.y := a
+    a <= UInt(1)
+    w.y <= a