Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit and removing Null and initialize-register pass

1 files changed, 21 insertions, 0 deletions

diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
new file mode 100644
index 00000000..9021d0c2
--- /dev/null
+++ b/test/passes/lower-to-ground/register.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl %s abcdefghi c | tee %s.out | FileCheck %s 
+
+; CHECK: Lower To Ground
+         circuit top :
+            module top :
+               input a : UInt(16)
+               input b : UInt(16)
+               output z : UInt
+
+               reg r1 : { x : UInt, flip y : SInt }
+               wire q : { x : UInt, flip y : SInt }
+               r1.init := q    
+
+      ; CHECK: reg r1#x : UInt
+      ; CHECK: reg r1#y : SInt
+      ; CHECK: wire q#x : UInt
+      ; CHECK: wire q#y : SInt
+      ; CHECK: r1#init#x := q#x
+      ; CHECK: q#y := r1#init#y
+
+; CHECK: Finished Lower To Ground