Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters

7 files changed, 43 insertions, 43 deletions

diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index f15980b3..29663234 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -1,8 +1,8 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
-   module m :
+   module top :
       wire i : UInt<2>
       wire j : UInt<32>
 
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index a4ba1eab..0b9d9799 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -1,10 +1,10 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
-   module q :
+   module top :
       wire i : UInt
-      wire j : UInt
+      wire j : { x : UInt<32>, flip y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
       ; CHECK: wire a$0$x : UInt<32>
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index 722d569c..c0acfecd 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -1,42 +1,42 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s
 
 circuit top :
    module m :
-      input  a : { x : UInt, flip y: SInt}
-      output b : { x : UInt, flip y: SInt}
-   module subtracter :
-      input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } }
-      wire a : { x : UInt, flip y : SInt}
-      wire b : { x : UInt, flip y : SInt}
+      input  a : { x : UInt<5>, flip y: SInt<5>}
+      output b : { x : UInt<5>, flip y: SInt<5>}
+   module top :
+      input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } }
+      wire a : { x : UInt<5>, flip y : SInt<5>}
+      wire b : { x : UInt<5>, flip y : SInt<5>}
       a := b
       inst i of m
       i.a := a
       b := i.b
-      wire d : UInt[5]
+      wire d : UInt<5>[5]
 
 ;CHECK: Lower To Ground
 ;CHECK: circuit top :
 ;CHECK:    module m :
-;CHECK:       input a$x : UInt
-;CHECK:       output a$y : SInt
-;CHECK:       output b$x : UInt
-;CHECK:       input b$y : SInt
+;CHECK:       input a$x : UInt<5>
+;CHECK:       output a$y : SInt<5>
+;CHECK:       output b$x : UInt<5>
+;CHECK:       input b$y : SInt<5>
 ;CHECK:       input reset : UInt<1>
-;CHECK:    module subtracter :
-;CHECK:       input c$x$0 : UInt
-;CHECK:       input c$x$1 : UInt
-;CHECK:       input c$x$2 : UInt
-;CHECK:       input c$x$3 : UInt
-;CHECK:       input c$x$4 : UInt
-;CHECK:       output c$y$x$0 : UInt
-;CHECK:       output c$y$x$1 : UInt
-;CHECK:       output c$y$x$2 : UInt
-;CHECK:       input c$y$y : SInt
+;CHECK:    module top :
+;CHECK:       input c$x$0 : UInt<5>
+;CHECK:       input c$x$1 : UInt<5>
+;CHECK:       input c$x$2 : UInt<5>
+;CHECK:       input c$x$3 : UInt<5>
+;CHECK:       input c$x$4 : UInt<5>
+;CHECK:       output c$y$x$0 : UInt<5>
+;CHECK:       output c$y$x$1 : UInt<5>
+;CHECK:       output c$y$x$2 : UInt<5>
+;CHECK:       input c$y$y : SInt<5>
 ;CHECK:       input reset : UInt<1>
-;CHECK:       wire a$x : UInt
-;CHECK:       wire a$y : SInt
-;CHECK:       wire b$x : UInt
-;CHECK:       wire b$y : SInt
+;CHECK:       wire a$x : UInt<5>
+;CHECK:       wire a$y : SInt<5>
+;CHECK:       wire b$x : UInt<5>
+;CHECK:       wire b$y : SInt<5>
 ;CHECK:       a$x := b$x
 ;CHECK:       b$y := a$y
 ;CHECK:       inst i of m
@@ -45,9 +45,9 @@ circuit top :
 ;CHECK:       a$y := i.a$y
 ;CHECK:       b$x := i.b$x
 ;CHECK:       i.b$y := b$y
-;CHECK:       wire d$0 : UInt
-;CHECK:       wire d$1 : UInt
-;CHECK:       wire d$2 : UInt
-;CHECK:       wire d$3 : UInt
-;CHECK:       wire d$4 : UInt
+;CHECK:       wire d$0 : UInt<5>
+;CHECK:       wire d$1 : UInt<5>
+;CHECK:       wire d$2 : UInt<5>
+;CHECK:       wire d$3 : UInt<5>
+;CHECK:       wire d$4 : UInt<5>
 ;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 4cd9f0cc..420c3c7c 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cdg | tee %s.out | FileCheck %s
 
 circuit top :
    module source :
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 95b125f6..b7915c5d 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -1,8 +1,8 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
 circuit top :
-   module q :
+   module top :
       wire i : UInt
       wire j : { x : UInt<32>, flip y : UInt<32> }
       wire k : { x : UInt<32>, y : UInt<32> }
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 918710a5..a3c4f0ae 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 
 ; CHECK: Lower To Ground
          circuit top :
diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir
index 5f5f37fb..7fcf0013 100644
--- a/test/passes/lower-to-ground/test.fir
+++ b/test/passes/lower-to-ground/test.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x X -p cdt | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p cdt | tee %s.out | FileCheck %s
 ; CHECK: Done!
 
 circuit Top :
@@ -8,6 +8,6 @@ circuit Top :
     output this : {out : {valid : UInt<1>, flip ready : UInt<1>}}
     inst queue of Queue
     this.out := queue.out
-    wire w : { x : UInt, flip y : UInt}
-    wire a : UInt
+    wire w : { x : UInt<5>, flip y : UInt<5>}
+    wire a : UInt<5>
     w.y := a