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authorazidar2016-01-26 14:18:34 -0800
committerazidar2016-01-28 09:25:04 -0800
commit5ab30c681558d2a26000696e518ee5b28deb1303 (patch)
treedcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/lower-to-ground/register.fir
parent8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff)
Updated all tests to pass
Diffstat (limited to 'test/passes/lower-to-ground/register.fir')
-rw-r--r--test/passes/lower-to-ground/register.fir9
1 files changed, 6 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 66d1cfb3..648964bd 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,11 +11,14 @@
wire q : { x : UInt, y : SInt }
q.x <= UInt(0)
q.y <= SInt(0)
- reg r1 : { x : UInt, y : SInt },clk,reset,q
+ reg r1 : { x : UInt, y : SInt } clk with :
+ reset => (reset,q)
; CHECK: wire q{{[_$]+}}x : UInt
; CHECK: wire q{{[_$]+}}y : SInt
- ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk, reset, q_x
- ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk, reset, q_y
+ ; CHECK: reg r1{{[_$]+}}x : UInt<1>, clk with :
+ ;CHECK: reset => (reset, q_x)
+ ; CHECK: reg r1{{[_$]+}}y : SInt<1>, clk with :
+ ;CHECK: reset => (reset, q_y)
; CHECK: Finished Lower Types