diff options
| author | azidar | 2015-05-20 01:35:15 -0700 |
|---|---|---|
| committer | azidar | 2015-05-20 01:35:15 -0700 |
| commit | ed04a9040f20c5e04880a18ec036c1a641443c50 (patch) | |
| tree | cb9cd4db719484c0a8ea52054915841bc8e0eb14 /test/passes/lower-to-ground/nested-vec.fir | |
| parent | 92e7da031a14df41ee0cab13a4a63b472fbdb5e1 (diff) | |
Added Pad pass to flo.stanza, which pads widths to make := and primops strict. Have not tested this
Diffstat (limited to 'test/passes/lower-to-ground/nested-vec.fir')
| -rw-r--r-- | test/passes/lower-to-ground/nested-vec.fir | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index b7915c5d..1a6ba2e8 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -8,29 +8,29 @@ circuit top : wire k : { x : UInt<32>, y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] - ; CHECK: wire a$0$x : UInt<32> - ; CHECK: wire a$0$y : UInt<32> - ; CHECK: wire a$1$x : UInt<32> - ; CHECK: wire a$1$y : UInt<32> + ; CHECK: wire a_0_x : UInt<32> + ; CHECK: wire a_0_y : UInt<32> + ; CHECK: wire a_1_x : UInt<32> + ; CHECK: wire a_1_y : UInt<32> accessor b = a[i] - ; CHECK: wire b$x : UInt<32> - ; CHECK: wire b$y : UInt<32> - ; CHECK: b$x := (a$0$x a$1$x)[i] - ; CHECK: (a$0$y a$1$y)[i] := b$y + ; CHECK: wire b_x : UInt<32> + ; CHECK: wire b_y : UInt<32> + ; CHECK: b_x := (a_0_x a_1_x)[i] + ; CHECK: (a_0_y a_1_y)[i] := b_y j := b mem m : { x : UInt<32>, y : UInt<32> }[2] - ; CHECK: mem m$x : UInt<32>[2] - ; CHECK: mem m$y : UInt<32>[2] + ; CHECK: mem m_x : UInt<32>[2] + ; CHECK: mem m_y : UInt<32>[2] accessor c = m[i] ; MALE - ; CHECK: accessor c$x = m$x[i] - ; CHECK: accessor c$y = m$y[i] + ; CHECK: accessor c_x = m_x[i] + ; CHECK: accessor c_y = m_y[i] c := k - ; CHECK: c$x := k$x - ; CHECK: c$y := k$y + ; CHECK: c_x := k_x + ; CHECK: c_y := k_y ; CHECK: Finished Lower To Ground |