diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/lower-to-ground/nested-vec.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/lower-to-ground/nested-vec.fir')
| -rw-r--r-- | test/passes/lower-to-ground/nested-vec.fir | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index aa208b01..0c58f267 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -17,7 +17,7 @@ circuit top : infer accessor b = a[i] ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> - j := b + j <= b cmem m : { x : UInt<32>, y : UInt<32> }[2],clk ; CHECK: cmem m{{[_$]+}}x : UInt<32>[2] @@ -27,9 +27,9 @@ circuit top : ; CHECK: accessor c{{[_$]+}}x = m{{[_$]+}}x[i] ; CHECK: accessor c{{[_$]+}}y = m{{[_$]+}}y[i] - c := k - ; CHECK: c{{[_$]+}}x := k{{[_$]+}}x - ; CHECK: c{{[_$]+}}y := k{{[_$]+}}y + c <= k + ; CHECK: c{{[_$]+}}x <= k{{[_$]+}}x + ; CHECK: c{{[_$]+}}y <= k{{[_$]+}}y ; CHECK: Finished Lower To Ground |