New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

1 files changed, 9 insertions, 9 deletions

diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 8d6beb93..ecc2d40b 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -4,7 +4,7 @@ circuit top :
    module source :
       output data : UInt<16>
       input ready : UInt<1>
-      data := UInt(16)
+      data <= UInt(16)
    module sink :
       input data : UInt<16>
       output ready : UInt<1>
@@ -13,23 +13,23 @@ circuit top :
       wire connect2 : { flip data : UInt<16>, ready: UInt<1> }
       inst src of source         
       inst snk of sink           
-      connect := src   
-      connect2 := snk
+      connect <= src   
+      connect2 <= snk
 
 
 ; CHECK: Resolve Genders
 
-; CHECK: connect@<g:f> := src@<g:m>
-; CHECK: connect2@<g:f> := snk@<g:m>
+; CHECK: connect@<g:f> <= src@<g:m>
+; CHECK: connect2@<g:f> <= snk@<g:m>
 
 ; CHECK: Finished Resolve Genders
 
 
 ; CHECK: Lower To Ground
 
-; CHECK: connect{{[_$]+}}data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect{{[_$]+}}ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2{{[_$]+}}data@<g:m>
-; CHECK: connect2{{[_$]+}}ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m>
+; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Lower To Ground