diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/lower-to-ground/instance.fir | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/lower-to-ground/instance.fir')
| -rw-r--r-- | test/passes/lower-to-ground/instance.fir | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index ecc2d40b..e0175f34 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -8,9 +8,14 @@ circuit top : module sink : input data : UInt<16> output ready : UInt<1> + ready <= UInt(1) module top: wire connect : { data : UInt<16>, flip ready: UInt<1> } + connect.ready <= UInt(1) + connect.data <= UInt(1) wire connect2 : { flip data : UInt<16>, ready: UInt<1> } + connect2.ready <= UInt(1) + connect2.data <= UInt(1) inst src of source inst snk of sink connect <= src @@ -25,11 +30,12 @@ circuit top : ; CHECK: Finished Resolve Genders -; CHECK: Lower To Ground +; CHECK: Lower Types ; CHECK: connect{{[_$]+}}data@<g:f> <= src@<g:m>.data@<g:m> +; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> ; CHECK: src@<g:m>.ready@<g:f> <= connect{{[_$]+}}ready@<g:m> ; CHECK: snk@<g:m>.data@<g:f> <= connect2{{[_$]+}}data@<g:m> -; CHECK: connect2{{[_$]+}}ready@<g:f> <= snk@<g:m>.ready@<g:m> -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types +; CHECK: Done! |