diff options
| author | azidar | 2015-05-27 15:43:15 -0700 |
|---|---|---|
| committer | azidar | 2015-05-27 15:43:15 -0700 |
| commit | a2a48576534f87b28566504bb1e0c7faa493f463 (patch) | |
| tree | 9fd3ce5825922c50c38507a1b0fc1e070bb9a481 /test/passes/lower-to-ground/bundle.fir | |
| parent | cf80ff9c83c2fedd42ec186a3e342520c89f91ab (diff) | |
Added external modules. Switched lower firrtl back to wire r; r := Register, instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
Diffstat (limited to 'test/passes/lower-to-ground/bundle.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index e758acaf..c0acfecd 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -17,37 +17,37 @@ circuit top : ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a_x : UInt<5> -;CHECK: output a_y : SInt<5> -;CHECK: output b_x : UInt<5> -;CHECK: input b_y : SInt<5> +;CHECK: input a$x : UInt<5> +;CHECK: output a$y : SInt<5> +;CHECK: output b$x : UInt<5> +;CHECK: input b$y : SInt<5> ;CHECK: input reset : UInt<1> ;CHECK: module top : -;CHECK: input c_x_0 : UInt<5> -;CHECK: input c_x_1 : UInt<5> -;CHECK: input c_x_2 : UInt<5> -;CHECK: input c_x_3 : UInt<5> -;CHECK: input c_x_4 : UInt<5> -;CHECK: output c_y_x_0 : UInt<5> -;CHECK: output c_y_x_1 : UInt<5> -;CHECK: output c_y_x_2 : UInt<5> -;CHECK: input c_y_y : SInt<5> +;CHECK: input c$x$0 : UInt<5> +;CHECK: input c$x$1 : UInt<5> +;CHECK: input c$x$2 : UInt<5> +;CHECK: input c$x$3 : UInt<5> +;CHECK: input c$x$4 : UInt<5> +;CHECK: output c$y$x$0 : UInt<5> +;CHECK: output c$y$x$1 : UInt<5> +;CHECK: output c$y$x$2 : UInt<5> +;CHECK: input c$y$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: wire a_x : UInt<5> -;CHECK: wire a_y : SInt<5> -;CHECK: wire b_x : UInt<5> -;CHECK: wire b_y : SInt<5> -;CHECK: a_x := b_x -;CHECK: b_y := a_y +;CHECK: wire a$x : UInt<5> +;CHECK: wire a$y : SInt<5> +;CHECK: wire b$x : UInt<5> +;CHECK: wire b$y : SInt<5> +;CHECK: a$x := b$x +;CHECK: b$y := a$y ;CHECK: inst i of m ;CHECK: i.reset := reset -;CHECK: i.a_x := a_x -;CHECK: a_y := i.a_y -;CHECK: b_x := i.b_x -;CHECK: i.b_y := b_y -;CHECK: wire d_0 : UInt<5> -;CHECK: wire d_1 : UInt<5> -;CHECK: wire d_2 : UInt<5> -;CHECK: wire d_3 : UInt<5> -;CHECK: wire d_4 : UInt<5> +;CHECK: i.a$x := a$x +;CHECK: a$y := i.a$y +;CHECK: b$x := i.b$x +;CHECK: i.b$y := b$y +;CHECK: wire d$0 : UInt<5> +;CHECK: wire d$1 : UInt<5> +;CHECK: wire d$2 : UInt<5> +;CHECK: wire d$3 : UInt<5> +;CHECK: wire d$4 : UInt<5> ;CHECK: Finished Lower To Ground |