diff options
| author | azidar | 2015-05-18 16:04:58 -0700 |
|---|---|---|
| committer | azidar | 2015-05-18 16:04:58 -0700 |
| commit | 3336e6beb23e1ba883097eac0c0000269bf8ebfa (patch) | |
| tree | c97d9ba8d0e50476e2d32a150fe401cc7413cff8 /test/passes/lower-to-ground/bundle.fir | |
| parent | 2702e571040e7a07317b79f9c5cfdbd61b9ab2bf (diff) | |
Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
Diffstat (limited to 'test/passes/lower-to-ground/bundle.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 722d569c..c0acfecd 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -1,42 +1,42 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s circuit top : module m : - input a : { x : UInt, flip y: SInt} - output b : { x : UInt, flip y: SInt} - module subtracter : - input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } } - wire a : { x : UInt, flip y : SInt} - wire b : { x : UInt, flip y : SInt} + input a : { x : UInt<5>, flip y: SInt<5>} + output b : { x : UInt<5>, flip y: SInt<5>} + module top : + input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } + wire a : { x : UInt<5>, flip y : SInt<5>} + wire b : { x : UInt<5>, flip y : SInt<5>} a := b inst i of m i.a := a b := i.b - wire d : UInt[5] + wire d : UInt<5>[5] ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a$x : UInt -;CHECK: output a$y : SInt -;CHECK: output b$x : UInt -;CHECK: input b$y : SInt +;CHECK: input a$x : UInt<5> +;CHECK: output a$y : SInt<5> +;CHECK: output b$x : UInt<5> +;CHECK: input b$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: module subtracter : -;CHECK: input c$x$0 : UInt -;CHECK: input c$x$1 : UInt -;CHECK: input c$x$2 : UInt -;CHECK: input c$x$3 : UInt -;CHECK: input c$x$4 : UInt -;CHECK: output c$y$x$0 : UInt -;CHECK: output c$y$x$1 : UInt -;CHECK: output c$y$x$2 : UInt -;CHECK: input c$y$y : SInt +;CHECK: module top : +;CHECK: input c$x$0 : UInt<5> +;CHECK: input c$x$1 : UInt<5> +;CHECK: input c$x$2 : UInt<5> +;CHECK: input c$x$3 : UInt<5> +;CHECK: input c$x$4 : UInt<5> +;CHECK: output c$y$x$0 : UInt<5> +;CHECK: output c$y$x$1 : UInt<5> +;CHECK: output c$y$x$2 : UInt<5> +;CHECK: input c$y$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: wire a$x : UInt -;CHECK: wire a$y : SInt -;CHECK: wire b$x : UInt -;CHECK: wire b$y : SInt +;CHECK: wire a$x : UInt<5> +;CHECK: wire a$y : SInt<5> +;CHECK: wire b$x : UInt<5> +;CHECK: wire b$y : SInt<5> ;CHECK: a$x := b$x ;CHECK: b$y := a$y ;CHECK: inst i of m @@ -45,9 +45,9 @@ circuit top : ;CHECK: a$y := i.a$y ;CHECK: b$x := i.b$x ;CHECK: i.b$y := b$y -;CHECK: wire d$0 : UInt -;CHECK: wire d$1 : UInt -;CHECK: wire d$2 : UInt -;CHECK: wire d$3 : UInt -;CHECK: wire d$4 : UInt +;CHECK: wire d$0 : UInt<5> +;CHECK: wire d$1 : UInt<5> +;CHECK: wire d$2 : UInt<5> +;CHECK: wire d$3 : UInt<5> +;CHECK: wire d$4 : UInt<5> ;CHECK: Finished Lower To Ground |