diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/lower-to-ground/bundle.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/passes/lower-to-ground/bundle.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 06558e44..ccf942ee 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -8,10 +8,10 @@ circuit top : input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } wire a : { x : UInt<5>, flip y : SInt<5>} wire b : { x : UInt<5>, flip y : SInt<5>} - a := b + a <= b inst i of m - i.a := a - b := i.b + i.a <= a + b <= i.b wire d : UInt<5>[5] ;CHECK: Lower To Ground @@ -35,13 +35,13 @@ circuit top : ;CHECK: wire a{{[_$]+}}y : SInt<5> ;CHECK: wire b{{[_$]+}}x : UInt<5> ;CHECK: wire b{{[_$]+}}y : SInt<5> -;CHECK: a{{[_$]+}}x := b{{[_$]+}}x -;CHECK: b{{[_$]+}}y := a{{[_$]+}}y +;CHECK: a{{[_$]+}}x <= b{{[_$]+}}x +;CHECK: b{{[_$]+}}y <= a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x -;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y -;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x -;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y +;CHECK: i.a{{[_$]+}}x <= a{{[_$]+}}x +;CHECK: a{{[_$]+}}y <= i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x <= i.b{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y <= b{{[_$]+}}y ;CHECK: wire d{{[_$]+}}0 : UInt<5> ;CHECK: wire d{{[_$]+}}1 : UInt<5> ;CHECK: wire d{{[_$]+}}2 : UInt<5> |