diff options
| author | azidar | 2015-07-30 11:50:54 -0700 |
|---|---|---|
| committer | azidar | 2015-07-30 11:50:54 -0700 |
| commit | 9b2f96b8d0b6c7f4e6fefde918d7a335ccd7b7f3 (patch) | |
| tree | 089578809d3ebe63ac5983ddda7fff7a6c00430a /test/passes/lower-to-ground/bundle.fir | |
| parent | d075e52e86648d345e89ae4a4c75fd3a98cc2788 (diff) | |
Updated lots of tests so they pass. Found one bug in expand whens
Diffstat (limited to 'test/passes/lower-to-ground/bundle.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 7c11cbc5..83318e10 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -17,34 +17,34 @@ circuit top : ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a_x : UInt<5> -;CHECK: output a_y : SInt<5> -;CHECK: output b_x : UInt<5> -;CHECK: input b_y : SInt<5> +;CHECK: input a{{[_$]+}}x : UInt<5> +;CHECK: output a{{[_$]+}}y : SInt<5> +;CHECK: output b{{[_$]+}}x : UInt<5> +;CHECK: input b{{[_$]+}}y : SInt<5> ;CHECK: module top : -;CHECK: input c_x_0 : UInt<5> -;CHECK: input c_x_1 : UInt<5> -;CHECK: input c_x_2 : UInt<5> -;CHECK: input c_x_3 : UInt<5> -;CHECK: input c_x_4 : UInt<5> -;CHECK: output c_y_x_0 : UInt<5> -;CHECK: output c_y_x_1 : UInt<5> -;CHECK: output c_y_x_2 : UInt<5> -;CHECK: input c_y_y : SInt<5> -;CHECK: wire a_x : UInt<5> -;CHECK: wire a_y : SInt<5> -;CHECK: wire b_x : UInt<5> -;CHECK: wire b_y : SInt<5> -;CHECK: a_x := b_x -;CHECK: b_y := a_y +;CHECK: input c{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}3 : UInt<5> +;CHECK: input c{{[_$]+}}x{{[_$]+}}4 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}0 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}1 : UInt<5> +;CHECK: output c{{[_$]+}}y{{[_$]+}}x{{[_$]+}}2 : UInt<5> +;CHECK: input c{{[_$]+}}y{{[_$]+}}y : SInt<5> +;CHECK: wire a{{[_$]+}}x : UInt<5> +;CHECK: wire a{{[_$]+}}y : SInt<5> +;CHECK: wire b{{[_$]+}}x : UInt<5> +;CHECK: wire b{{[_$]+}}y : SInt<5> +;CHECK: a{{[_$]+}}x := b{{[_$]+}}x +;CHECK: b{{[_$]+}}y := a{{[_$]+}}y ;CHECK: inst i of m -;CHECK: i.a_x := a_x -;CHECK: a_y := i.a_y -;CHECK: b_x := i.b_x -;CHECK: i.b_y := b_y -;CHECK: wire d_0 : UInt<5> -;CHECK: wire d_1 : UInt<5> -;CHECK: wire d_2 : UInt<5> -;CHECK: wire d_3 : UInt<5> -;CHECK: wire d_4 : UInt<5> +;CHECK: i.a{{[_$]+}}x := a{{[_$]+}}x +;CHECK: a{{[_$]+}}y := i.a{{[_$]+}}y +;CHECK: b{{[_$]+}}x := i.b{{[_$]+}}x +;CHECK: i.b{{[_$]+}}y := b{{[_$]+}}y +;CHECK: wire d{{[_$]+}}0 : UInt<5> +;CHECK: wire d{{[_$]+}}1 : UInt<5> +;CHECK: wire d{{[_$]+}}2 : UInt<5> +;CHECK: wire d{{[_$]+}}3 : UInt<5> +;CHECK: wire d{{[_$]+}}4 : UInt<5> ;CHECK: Finished Lower To Ground |