diff options
| author | azidar | 2016-01-07 17:15:31 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:18 -0800 |
| commit | 4569194392122ae4715549b2f0b9fffff051b278 (patch) | |
| tree | ecd079cefa6fb69d1f8c75bc0e75e38599bc0da4 /test/passes/lower-to-ground/bundle.fir | |
| parent | 2d583abda146dad8e0260928dcb19ad7136216b6 (diff) | |
Fixed a bunch of tests, and minor bugs
Diffstat (limited to 'test/passes/lower-to-ground/bundle.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle.fir | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index b2ea2d63..a8f8ad78 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -4,7 +4,7 @@ circuit top : module m : input a : { x : UInt<5>, flip y: SInt<5>} output b : { x : UInt<5>, flip y: SInt<5>} - a.y <= UInt(0) + a.y <= SInt(0) b.x <= UInt(0) module top : input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } |