diff options
| author | azidar | 2016-01-26 14:18:34 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:04 -0800 |
| commit | 5ab30c681558d2a26000696e518ee5b28deb1303 (patch) | |
| tree | dcdfaeb3bcb42561e010928712218c8cd3a1b2c7 /test/passes/lower-to-ground/bundle-vecs.fir | |
| parent | 8c288f7b159b3f4ca1cb0d5c5012eb8fb52d5214 (diff) | |
Updated all tests to pass
Diffstat (limited to 'test/passes/lower-to-ground/bundle-vecs.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index 64a4a4b6..c42766ad 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -25,19 +25,19 @@ circuit top : ;CHECK: wire GEN_3 : UInt<32> ;CHECK: j_x <= GEN_0 ;CHECK: j_y <= GEN_3 -;CHECK: node GEN_4 = eqv(UInt("h0"), i) +;CHECK: node GEN_4 = eq(UInt("h0"), i) ;CHECK: a_0_x <= mux(GEN_4, GEN_2, UInt("h0")) -;CHECK: node GEN_5 = eqv(UInt("h0"), i) +;CHECK: node GEN_5 = eq(UInt("h0"), i) ;CHECK: a_0_y <= mux(GEN_5, GEN_1, UInt("h0")) -;CHECK: node GEN_6 = eqv(UInt("h1"), i) +;CHECK: node GEN_6 = eq(UInt("h1"), i) ;CHECK: a_1_x <= mux(GEN_6, GEN_2, UInt("h0")) -;CHECK: node GEN_7 = eqv(UInt("h1"), i) +;CHECK: node GEN_7 = eq(UInt("h1"), i) ;CHECK: a_1_y <= mux(GEN_7, GEN_1, UInt("h0")) -;CHECK: node GEN_8 = eqv(UInt("h1"), i) +;CHECK: node GEN_8 = eq(UInt("h1"), i) ;CHECK: GEN_0 <= mux(GEN_8, a_1_x, a_0_x) ;CHECK: GEN_1 <= j_y ;CHECK: GEN_2 <= j_x -;CHECK: node GEN_9 = eqv(UInt("h1"), i) +;CHECK: node GEN_9 = eq(UInt("h1"), i) ;CHECK: GEN_3 <= mux(GEN_9, a_1_y, a_0_y) ; CHECK: Finished Lower Types |