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authorazidar2015-05-18 16:04:58 -0700
committerazidar2015-05-18 16:04:58 -0700
commit3336e6beb23e1ba883097eac0c0000269bf8ebfa (patch)
treec97d9ba8d0e50476e2d32a150fe401cc7413cff8 /test/passes/lower-to-ground/bundle-vecs.fir
parent2702e571040e7a07317b79f9c5cfdbd61b9ab2bf (diff)
Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
Diffstat (limited to 'test/passes/lower-to-ground/bundle-vecs.fir')
-rw-r--r--test/passes/lower-to-ground/bundle-vecs.fir6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index a4ba1eab..0b9d9799 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -1,10 +1,10 @@
-; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
; CHECK: Lower To Ground
circuit top :
- module q :
+ module top :
wire i : UInt
- wire j : UInt
+ wire j : { x : UInt<32>, flip y : UInt<32> }
wire a : { x : UInt<32>, flip y : UInt<32> }[2]
; CHECK: wire a$0$x : UInt<32>