diff options
| author | azidar | 2015-12-12 14:37:41 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (patch) | |
| tree | 42e8e2ed50a254f7fea61bc0a56d963258463bb5 /test/passes/lower-to-ground/bundle-vecs.fir | |
| parent | d9f33f58c94382dfbd22e87e2f85600b9807328f (diff) | |
WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadblock in assigning clocked ports
Diffstat (limited to 'test/passes/lower-to-ground/bundle-vecs.fir')
| -rw-r--r-- | test/passes/lower-to-ground/bundle-vecs.fir | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index b0de26f4..719033cb 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -1,9 +1,9 @@ ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s -; CHECK: Lower To Ground +; CHECK: Lower Types circuit top : module top : - wire i : UInt + input i : UInt<1> wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] @@ -11,17 +11,34 @@ circuit top : ; CHECK: wire a{{[_$]+}}0{{[_$]+}}y : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}x : UInt<32> ; CHECK: wire a{{[_$]+}}1{{[_$]+}}y : UInt<32> + a[0].x <= UInt(0) + a[0].y <= UInt(0) + a[1].x <= UInt(0) + a[1].y <= UInt(0) - infer accessor b = a[i] - ; CHECK: indexer b{{[_$]+}}x = (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] : UInt<32> - ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] = b{{[_$]+}}y : UInt<32> - j <= b - - infer accessor c = a[i] - ; CHECK: indexer (a{{[_$]+}}0{{[_$]+}}x a{{[_$]+}}1{{[_$]+}}x)[i] = c{{[_$]+}}x : UInt<32> - ; CHECK: indexer c{{[_$]+}}y = (a{{[_$]+}}0{{[_$]+}}y a{{[_$]+}}1{{[_$]+}}y)[i] : UInt<32> - c <= j + j <= a[i] + a[i] <= j +;CHECK: wire GEN : UInt<32> +;CHECK: wire GEN_1 : UInt<32> +;CHECK: wire GEN_2 : UInt<32> +;CHECK: wire GEN_3 : UInt<32> +;CHECK: j_x <= GEN +;CHECK: j_y <= GEN_3 +;CHECK: node a_0_x = eqv(UInt("h0"), i) +;CHECK: a_0_x <= mux(a_0_x, GEN_2, UInt("h0")) +;CHECK: node a_0_y = eqv(UInt("h0"), i) +;CHECK: a_0_y <= mux(a_0_y, GEN_1, UInt("h0")) +;CHECK: node a_1_x = eqv(UInt("h1"), i) +;CHECK: a_1_x <= mux(a_1_x, GEN_2, UInt("h0")) +;CHECK: node a_1_y = eqv(UInt("h1"), i) +;CHECK: a_1_y <= mux(a_1_y, GEN_1, UInt("h0")) +;CHECK: node GEN_4 = eqv(UInt("h1"), i) +;CHECK: GEN <= mux(GEN_4, a_1_x, a_0_x) +;CHECK: GEN_1 <= j_y +;CHECK: GEN_2 <= j_x +;CHECK: node GEN_5 = eqv(UInt("h1"), i) +;CHECK: GEN_3 <= mux(GEN_5, a_1_y, a_0_y) -; CHECK: Finished Lower To Ground +; CHECK: Finished Lower Types |