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authorazidar2015-12-09 18:31:45 -0800
committerazidar2016-01-16 14:28:17 -0800
commitbe78d49aa01c097978f69a3b022acb2047fdf438 (patch)
tree76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/passes/lower-to-ground/accessor.fir
parentc427b31a1ef8361b643d5f7435aeb42472dfe626 (diff)
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
Diffstat (limited to 'test/passes/lower-to-ground/accessor.fir')
-rw-r--r--test/passes/lower-to-ground/accessor.fir8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 4d55d0f6..c712fdc2 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -15,18 +15,18 @@ circuit top :
infer accessor b = a[i]
; CHECK: indexer b = (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] : UInt<32>
- j := b
+ j <= b
infer accessor c = a[i]
; CHECK: indexer (a{{[_$]+}}0 a{{[_$]+}}1 a{{[_$]+}}2 a{{[_$]+}}3)[i] = c : UInt<32>
- c := j
+ c <= j
cmem p : UInt<32>[4],clk
infer accessor t = p[i]
; CHECK: read accessor t = p[i]
- j := t
+ j <= t
infer accessor r = p[i]
; CHECK: write accessor r = p[i]
- r := j
+ r <= j
; CHECK: Finished Lower To Ground